adv7150 Analog Devices, Inc., adv7150 Datasheet - Page 21

• Manufacturer Part Number: adv7150
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

Palette Select Match Bits Control (MR17–MR16)
These bits allow multiple palette devices to work together.
When bits PS1 and PS0 match MR17 and MR16 respectively,
the device is selected. If these bits do not match, the device is
not selected and the analog video outputs drive 0 mA, see
“Palette Priority Select Inputs” section.
CONTROL REGISTERS
The ADV7150 has 9 control registers. To access each register,
two write operations must be performed. The first write to the
address register specifies which of the 9 registers is to be ac-
cessed. The second access determines the value written to that
particular control register.
Pixel Test Register
(Address Reg (A7–A0) = 00H)
This register is used when the device is in test/diagnostic mode.
It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide
read-only register which allows the MPU to read data on the
pixel port, see “Test Diagnostic” section.
DAC Test Register
(Address Reg (A7–A0) = 01H)
This register is used when the device is in test/diagnostic mode.
It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide
read-only register which allows MPU access to the DAC port,
see “Test Diagnostic” section.
SYNC, BLANK and I
(Address Reg (A7–A0) = 02H)
This register is used when the device is in test/diagnostic mode.
It is a 3-bit wide (3 LSBs) read/write register which allows MPU
access to these particular pixel control bits, see “Test Diagnos-
tic” section.
REV. A
*THESE BITS ARE
READ–ONLY
RESERVED BITS.
RETURN ZEROS "00."
A READ CYCLE WILL
PLL
CR19
RESERVED*
Test Register
CR18
CR17
THESE BITS SHOULD
BE SET TO ZERO
Command Register 1 (CR1) (CR19–CR10)
CR17-CR13
(00000)
CR16
SYNCOUT CONTROL
CR12
CR15
0
1
–21–
DISABLE
ENABLE
SYNCOUT
ID Register
(Address Reg (A7–A0) = 03H)
This is an 8-bit wide “Identification” read-only register. For the
ADV7150 it will always return the hexadecimal value 8EH.
Pixel Mask Register
(Address Reg (A7–A0) = 04H)
The contents of the pixel mask register are individually bit-wise
logically AND-ed with the Red, Green and Blue pixel input
stream of data. It is an 8-bit read/write register with D0 corre-
sponding to R0, G0 and B0. For normal operation, this register
is set with FFH.
COMMAND REGISTER 1 (CR1)
(Address Reg (A7–A0) = 05H)
This register contains a number of control bits as shown in the
diagram. CR1 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR18 to CR19 are reserved).
The diagram below shows the various operations under the con-
trol of CR1. This register can be read from as well as written to. In
write mode, “0” should be written to CR11 and CR13 to CR17.
In read mode, CR11 and CR13 to CR19 are returned as zeros.
COMMAND REGISTER 1-BIT DESCRIPTION
Calibration Control (CR10)
This bit automatically calibrates the onboard LOADIN/
LOADOUT synchronization circuit. MR15 of Mode Register
MR1 must be set to “0.”
SYNCOUT Control (CR12)
This bit specified whether the video SYNCOUT signal is to be
enabled. On power up a “0” is written to the bit and
“SYNCOUT” is set three-state.
CR14
CR13
CR10
THIS BIT SHOULD BE
SET TO ZERO
0
1
CALIBRATION CONTROL
CR12
CR11
DISABLE
CALIBRATES ON EVERY
VERTICAL SYNC (MR15=0)
(0)
CR11
CR10
ADV7150