adv7150 Analog Devices, Inc., adv7150 Datasheet - Page 27

• Manufacturer Part Number: adv7150
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

Digital Signal Interconnect
The digital inputs to the ADV7150 should be isolated as much
as possible from the analog outputs and other analog circuitry.
Also, these input signals should not overlay the analog power
plane.
Due to the high clock rates involved, long clock lines to the
ADV7150 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
analog power plane.
Analog Signal Interconnect
The ADV7150 should be located as close as possible to the out-
put connectors to minimize noise pick-up and reflections due to
impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
REV. A
CONTROLLER
PROCESSOR/
MEMORY
BUFFER/
GRAPHICS
FRAME
VIDEO
GENERATOR
CLOCK
CLOCK
(BANK D)
(BANK C)
(BANK A)
(BANK B)
BLANK
SYNC
VRAM
VRAM
VRAM
VRAM
CC
TYPICAL FRAME BUFFER INTERFACE
), and not the
33MHz
33MHz
33MHz
33MHz
PRGCKOUT
SCKOUT
LOADOUT
SCKIN
LOADIN
CLOCK
CLOCK
BLANK
APPENDIX 2
SYNC
24
24
24
24
–27–
Digital Inputs, especially Pixel Data Inputs and clocking signals
(CLOCK, LOADOUT, LOADIN, etc.) should never overlay
any of the analog signal circuitry and should be kept as far away
as possible.
For best performance, the analog outputs (IOR, IOG, IOB)
should each have a 75
These resistors should be placed as close as possible to the
ADV7150 so as to minimize reflections. Normally, the differen-
tial analog outputs (IOR, IOG, IOB) are connected directly to
GND. In some applications, improvements in performance are
achieved by terminating these differential outputs with a resis-
tive load similar in value to the video load. For a doubly termi-
nated 75
terminated with 37.5
24
24
24
24
ECL
TTL
TO
MULTIPLEXER
DIVIDE BY N
load, this means that IOR, IOG, IOB are each
( N)
24
LATCH
ENABLE
ADV7150
resistors.
DIVIDE BY M
load resistor connected to GND.
TO
PALETTE/RAM
& DAC
( M)
ADV7150