adv7340 Analog Devices, Inc., adv7340 Datasheet - Page 41

• Manufacturer Part Number: adv7340
• Description: Multiformat Video Encoder, Six 12-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

Table 27. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
1
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
Register
SD Timing Register 0
SD Timing Register 1
(Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1)
SD F
SD F
SD F
SD F
SD F
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
1
1
1
1
Bit Description
SD Slave/Master Mode.
SD Timing Mode.
Reserved.
SD Luma Delay.
SD Minimum Luma Value.
SD Timing Reset.
SD HSYNC Width.
SD HSYNC to VSYNC Delay.
SD HSYNC to VSYNC Rising
Edge Delay (Mode 1 Only).
SD VSYNC Width (Mode 2
Only).
SD HSYNC to Pixel Data
Adjust.
Subcarrier Frequency Bits[7:0].
Subcarrier Frequency Bits[15:8].
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24].
Subcarrier Phase Bits[9:2].
Extended Data on Even Fields.
Extended Data on Even Fields.
Data on Odd Fields.
Data on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Even Fields.
Pedestal on Even Fields.
Rev. 0 | Page 41 of 88
7
x
0
0
1
1
x
x
x
x
x
x
x
x
x
17
25
17
25
6
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
16
24
16
24
5
0
0
1
1
x
x
0
0
1
1
x
x
x
x
x
x
x
x
x
15
23
15
23
Bit Number
4
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
14
22
14
22
3
1
0
0
1
1
x
x
x
x
x
x
x
x
x
13
21
13
21
2
0
0
1
1
0
1
0
1
x
x
x
x
x
x
x
x
x
12
20
12
20
1
0
1
0
1
0
0
1
1
x
x
x
x
x
x
x
x
x
11
19
11
19
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
10
18
10
18
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
No delay.
2 clock cycles.
4 clock cycles.
6 clock cycles.
−40 IRE.
−7.5 IRE.
A low-high-low transition
resets the internal SD timing
counters.
t
t
t
t
t
t
t
t
t
t
1 clock cycle.
4 clock cycles.
16 clock cycles.
128 clock cycles.
0 clock cycles.
1 clock cycle.
2 clock cycles.
3 clock cycles.
Subcarrier Frequency Bits[7:0].
Subcarrier Frequency Bits[15:8].
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24].
Subcarrier Phase Bits[9:2].
Extended Data Bits[7:0].
Extended Data Bits[15:8].
Data Bits[7:0].
Data Bits[15:8].
Setting any of these bits to 1
disables pedestal on the line
number indicated by the bit
settings.
a
a
a
a
b
b
b
b
c
c
= 1 clock cycle.
= 4 clock cycles.
= 16 clock cycles.
= 128 clock cycles.
= t
= t
= 0 clock cycles.
= 4 clock cycles.
= 8 clock cycles.
= 18 clock cycles.
ADV7340/ADV7341
b
b
.
+ 32 μs.
Reset
Value
0x08
0x00
0x1F
0x7C
0xF0
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00