adv7340 Analog Devices, Inc., adv7340 Datasheet - Page 64

• Manufacturer Part Number: adv7340
• Description: Multiformat Video Encoder, Six 12-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

ADV7340/ADV7341
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For synchronization purposes, the ADV7340/ADV7341 are able to accept either time codes embedded in the input pixel data or external
synchronization signals provided on the S_HSYNC , S_VSYNC , P_HSYNC , P_VSYNC , and P_BLANK pins (see Table 49). It is also
possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52).
Table 49. Timing Synchronization Signal Input Options
Signal
SD HSYNC In
SD VSYNC In
ED/HD HSYNC In
ED/HD VSYNC In
ED/HD BLANK In
1
Table 50. Timing Synchronization Signal Output Options
Signal
SD HSYNC Out
SD VSYNC Out
ED/HD HSYNC Out
ED/HD VSYNC Out
1
Table 51. HSYNC Output Control
ED/HD Input Sync
Format (0x30, Bit 2)
x
x
0
1
x
1
Table 52. VSYNC Output Control
ED/HD Input
Sync Format
(0x30, Bit 2)
x
x
0
1
1
x
x
1
SD and ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02[7:6] = 00).
ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
ED/HD VSYNC
Control
(0x34, Bit 2)
X
X
0
0
0
1
1
ED/HD HSYNC
Control
(0x34, Bit 1)
x
x
0
0
1
Pin
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
Pin
S_HSYNC
S_VSYNC
S_HSYNC
S_VSYNC
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
1
1
1
1
1
1
1
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
1
1
1
Condition
SD Slave Timing Mode 1, 2, or 3 selected (Subaddress 0x8A[2:0]).
SD Slave Timing Mode 1, 2, or 3 selected (Subaddress 0x8A[2:0]).
ED/HD Timing Sync. Inputs enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Sync. Inputs enabled (Subaddress 0x30, Bit 2 = 0).
Condition
SD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 6 = 1).
SD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 6 = 1).
ED/HD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 7 = 1).
ED/HD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 7 = 1).
SD Sync
Output Enable
(0x02, Bit 6)
0
1
x
x
x
x
x
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SD Sync
Output Enable
(0x02, Bit 6)
0
1
x
x
x
Video Standard
x
Interlaced
x
All HD interlaced
standards
All ED/HD progressive
standards
All ED/HD standards
except 525p
525p
Signal on S_HSYNC Pin
Tristate.
Pipelined SD HSYNC.
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based
on AV Code H bit.
Pipelined ED/HD HSYNC based
on horizontal counter.
Signal on S_VSYNC Pin
Tristate.
Pipelined SD VSYNC/Field.
Pipelined ED/HD VSYNC
or field signal.
Pipelined field signal
based on AV Code F bit.
Pipelined VSYNC based on
AV Code V bit.
Pipelined ED/HD VSYNC
based on vertical counter.
Pipelined ED/HD VSYNC
based on vertical counter.
1
1
1
1
Duration
–
See
SD Timing
As per HSYNC
timing.
Same as line
blanking interval.
Same as embedded
HSYNC.
Duration
–
See
SD Timing
As per VSYNC or
field signal timing.
Field.
Vertical blanking
interval.
Aligned with
serration lines.
Vertical blanking
interval.
Appendix 5—
Appendix 5—
.
.