adv7340 Analog Devices, Inc., adv7340 Datasheet - Page 47

• Manufacturer Part Number: adv7340
• Description: Multiformat Video Encoder, Six 12-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

Whether the ED/HD Y data is clocked in upon the rising or
falling edge of CLKIN_B is determined by Subaddress 0x01,
Bits[2:1] (See the input sequence shown in Figure 52 and
Figure 53).
Figure 56. Simultaneous SD and HD Example Application
Figure 55. Simultaneous SD and ED Example Application
DECODER
DECODER
DECODER
DECODER
HD
SD
ED
SD
1080i
1035i
525p
625p
720p
OR
OR
OR
27MHz
74.25MHz
CrCb
27MHz
YCrCb
CrCb
Y
27MHz
YCrCb
CrCb
Y
10
10
10
10
3
3
10
10
2
2
S_VSYNC,
S_HSYNC
CLKIN_A
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
S_VSYNC,
S_HSYNC
CLKIN_A
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
ADV7340/
ADV7340/
ADV7341
ADV7341
Rev. 0 | Page 47 of 88
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the P_HSYNC ,
P_VSYNC , and P_BLANK pins.
The interleaved pixel data is input on Pin Y9 to Pin Y2/Y0, with
Y0 being the LSB in 10-bit input mode.
CLKIN_A
Y9–Y0
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
INTERLACED TO
Figure 58. ED Only (at 54 MHz) Example Application
PROGRESSIVE
DECO DER
3FF
MPEG2
YCrCb
00
54MHz
YCrCb
00
10
3
XY
ADV7340/ADV7341
P_HSYNC,
P_BLANK
CLKIN_A
Y[9:0]
P_VSYNC,
Cb0
ADV7340/
ADV7341
Y0
Cr0
Y1