mc33970 Freescale Semiconductor, Inc, mc33970 Datasheet - Page 7

• Manufacturer Part Number: mc33970
• Description: Dual Gauge Driver Integrated Circuit With Improved Damping Algorithms
• Manufacturer: Freescale Semiconductor, Inc

Table 4. Dynamic Electrical Characteristics
values noted reflect the approximate parameter means at T
POWER OUTPUT AND CLOCK TIMINGS
SPI INTERFACE TIMING
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
SIN, COS Output Turn ON Delay Time (Time from Rising
Outputs to Steady State Coil Voltages and Currents)
SIN, COS Output Turn OFF Delay Time (Time from Rising
Outputs to Steady State Coil Voltages and Currents)
Uncalibrated Oscillator Cycle Time
Calibrated Oscillator Cycle Time
Maximum Pointer Speed
Maximum Pointer Acceleration
Recommended Frequency of SPI Operation
Falling Edge of
Falling Edge of SCLK to Rising Edge of
SI to Falling Edge of SCLK (Required Setup Time)
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Hold Time)
SO Rise Time
SO Fall Time
SI,
SI,
Falling Edge of
Rising Edge of
Rising Edge of
14.
15.
16.
17.
18.
19.
Characteristics noted under conditions 4.75 V < V
Cal Pulse = 8.0 µs, PECCR D4 = Logic [0]
Cal pulse = 8.0 µs, PECCR D4 = Logic [1]
C
C
CS
CS
L
L
= 200 pF
= 200 pF
, SCLK, Incoming Signal Rise Time
, SCLK, Incoming Signal Fall Time
Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.
The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.
The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature
range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall
be fully functional for slower clock speeds. See
The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes
CS
RST
CS
RST
to Falling Edge of
to Rising Edge of SCLK (Required Setup Time)
to Falling Edge of
to Rising Edge of
(16)
(15)
Characteristic
(15)
CS
RST
CS
CS
DYNAMIC ELECTRICAL CHARACTERISTICS
(Required Setup Time)
(18)
(Required Setup Time)
(18)
(Required Setup Time)
(Required Setup Time)
(17)
(17)
(14)
(14)
Figure 4
DD
CS
CS
< 5.25 V, -40°C < T
Enabling
(17)
Disables
(17)
and 5.
(17),
(17)
A
(17)
(17)
(17)
= 25°C under nominal conditions unless otherwise noted.
(19)
t
t
t
A
Symbol
DLY (OFF)
t
t
SI
DLY (ON)
WSCLKH
WSCLKL
t
A
V
t
t
t
W
< 125°C, GND = 0 V unless otherwise noted. Typical
t
t
LEAD
t
t
(HOLD)
f
S
t
R
F
t
t
t
CLU
CLC
LAG
MAX
RSI
MAX
SPI
F
CS
EN
RST
ISU
SO
SO
SI
DYNAMIC ELECTRICAL CHARACTERISTICS
0.65
Min
1.0
0.9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ELECTRICAL CHARACTERISTICS
Typ
1.0
1.1
1.0
1.0
50
50
25
25
25
25
–
–
–
–
–
–
–
–
–
–
–
4500
Max
400
167
167
167
167
1.0
1.0
1.7
1.2
1.1
3.0
3.0
5.0
5.0
83
83
50
50
50
50
Unit
MHz
°/s
ms
ms
°/s
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
33970
2
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