mc33742 Freescale Semiconductor, Inc, mc33742 Datasheet - Page 27

• Manufacturer Part Number: mc33742
• Description: Mc33742 System Basis Chip Sbc With Enhanced High-speed Can Transceiver
• Manufacturer: Freescale Semiconductor, Inc

WATCHDOG SOFTWARE (RST AND WDOG)
(SELECTABLE WATCHDOG WINDOW OR
WATCHDOG TIME-OUT)
modes for monitoring the MCU operation. The watchdog
timer may be implemented as either a watchdog window or
watchdog time-out, selectable by SPI (TIM1 sub register, bit
WDW). Default operation is a watchdog window.
(TIM1 sub register, bits WDT0 and WDT1). When a watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of
the period. (Refer to
page 47.)
time period. Any attempt to clear watchdog in the closed
window will generate a reset. The watchdog is cleared
addressing the TIM1 sub register using the SPI
Table 8. Watchdog and Reset Output Operation
Analog Integrated Circuit Device Data
Freescale Semiconductor
Notes
41.
A watchdog is used in the SBC Normal and Standby
The watchdog period can be set from 10 ms to 350 ms
The watchdog can only be cleared within the open window
SPI Stop/Sleep
Command
WDOG stays LOW until the TIM1 register is properly addressed through SPI.
SPI CS
VDD Normal, WDOG Properly Triggered
WDOG Time-out Reached
Timing Register (TIM1 / 2)
Device Power-Up
VDD < V
Events
RSTTH
33742 in Normal
or Stand-by mode
Figure 11. Entering the Stop Mode
beginning on
t
CS-STOP
RST PIN DESCRIPTION
Reset can happen from:
RST AND WDOG OPERATION
operation. RST is activated in the event VDD fall or watchdog
is not triggered. WDOG output is active LOW as soon as RST
goes LOW and stays LOW as long as the watchdog is not
properly reset via SPI. The WDOG output pin is designed as
a push-pull structure that can drive off chip components
signaling, for instance, errant MCU operation.
TIM1 register in not properly accessed. In this case a
software reset occurs, and the WDOG pin is set LOW until
the TIM1 register is properly accessed.
No I
A 33742 output is available to perform a reset of the MCU.
• VDD Falling Out of Range — If VDD falls below the reset
• Power-ON Reset — At 33742 power-on or wake-up from
• Watchdog Time-out — If watchdog is not cleared, the
Table 8
Figure 12
33742 in Stop mode.
threshold (V
VDD returns to the normal voltage.
Sleep mode, the RST pin is maintained LOW until VDD
is within its operation range.
33742 will pull the RST pin LOW for the duration of the
reset time (t
LOW to HIGH
DD
LOW
Output
WDOG
HIGH
HIGH
tIDD-DGLT
over I
describes watchdog and reset output modes of
(41)
illustrates the device behavior in the event the
DD-DGLT
RSTDUR
RSTTH
), the RST pin is pulled LOW until
).
FUNCTIONAL DEVICE OPERATION
33742 in Stop mode.
I
DD
OPERATIONAL MODES
LOW to HIGH
over I
RST Output
HIGH
LOW
LOW
DD-DGLT
33742
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