mc33742 Freescale Semiconductor, Inc, mc33742 Datasheet - Page 51

• Manufacturer Part Number: mc33742
• Description: Mc33742 System Basis Chip Sbc With Enhanced High-speed Can Transceiver
• Manufacturer: Freescale Semiconductor, Inc

INTERRUPT REGISTER (INTR)
source. A read operation identifies the interrupt source.
register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR,
CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched
in the CAN register and the IOR register.
Table 40. Interrupt Register
Table 41. Interrupt Register Control Bits
due to overcurrent detection (I
(not bit set into the INTR register).
Table 42. Interrupt Register Status Bits
Analog Integrated Circuit Device Data
Freescale Semiconductor
Notes
64.
65.
Tables 40
When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode
Reset Condition
Reset Value
(Write)
If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.
See Table 13, page 42, for definitions of reset conditions.
$111b
INTR
VSUPLOW
VDDTEMP
HSOT - V2LOW
HSOT
Name
CANF
VSUPLOW
through
VDDTEMP
(65)
Name
CANF
42
contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt
R/W
W
R
–
–
DDS-WU1
Mask bit for CAN failures.
Mask bit for VDD medium temperature
(pre-warning).
Mask bit for HS overtemperature AND V
Mask bit for V
or I
Logic
POR, RST
DDS-WU2
VSUPLOW
VSUPLOW
0
1
0
1
0
1
0
1
D3
0
BF(EW)
), an INT pulse is generated; however, INTR register content remains at 0000
Table 42
< 5.8 V.
No V
V
No HS overtemperature.
HS overtemperature.
No VDD medium temperature (pre-warning).
VDD medium temperature (pre-warning).
No CAN failure.
CAN failure.
BF(EW)
HSOT-V2LOW
BF(EW)
provides status bit information. The status bits of the INTR
POR, RST
< 5.8 V.
HSOT
D2
(64)
0
< 5.8 V.
2LTH
Description
< 4.0 V.
Description
POR, RST
V1TEMP
V1TEMP
LOGIC COMMANDS AND REGISTERS
D1
0
FUNCTIONAL DEVICE OPERATION
POR, RST
CANF
CANF
D0
0
33742
51