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ICs for Communications Multichannel Network Interface Controller for HDLC MUNICH32 PEB 20320 Version 3.4 User’s Manual 01.2000 DS3 ...
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PEB 20320 Revision History: Current Version: 01.2000 Previous Version: User’s Manual 1998-06-01 DS2 (V3.4) Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Package P-TQFP-176-1 removed from User’s Manual. For questions on technology, delivery ...
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Preface The Multichannel Network Interface Controller for HDLC (MUNICH32 Multichannel Protocol Controller for a wide area of telecommunication and data communication applications. Organization of this Document This User’s Manual is divided into 9 chapters organized as ...
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User’s Manual PEB 20320 4 01.2000 ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.1.3.2 Hardware Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 5.1.4 Test ...
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Introduction The Multichannel Network Interface Controller for HDLC (MUNICH32 Multichannel Protocol Controller, which handles data channels of a full duplex PCM highway. It performs layer 2 HDLC formatting/deformatting or V.110 and X.30 protocols up ...
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Multichannel Network Interface Controller for HDLC MUNICH32 Version 3.4 1.1 Features • Serial Interface – independent communication channels. – Serial multiplexed (full duplex) input/output for 2048-, 4096-, 1544- or 1536-Kbit/s PCM highways. • Dynamic Programmable Channel Allocation ...
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V.110/X.30 Protocol – Automatic synchronization in receive direction, automatic generation of the synchronization pattern in transmit direction – bits freely programmable in transmit direction, van be changed during transmission; changes monitored and reported in ...
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General – Connection four MUNICH32 supporting a 128-channel basic access D-channel controller. – ON-CHIP receive and transmit data buffer; the buffer size is 256 bytes each. – HDLC protocol or transparent mode, support of ECMA 102, ...
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Pin Configuration (top view) 120 110 D8 121 D10 A10 130 D11 A11 D12 A12 D13 A13 V 140 ...
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Pin Definitions and Functions Pin Definitions and Functions Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 83, 87, 88, 92 97, 103, 104, 110, 111, 117, 123, 130, 136, 141, 144, 150, 151, 157 10, ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 33 A29 DP1 28 A28 DP0 26, 21, 19, 15, A(27:2) 13 160, 156, 154, 149, 147, 143, 139, 135, 133, 128, 126, 122, ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 38, 34, 32, 27, D(31:0) 25, 20, 18, 14, 12 159, 153, 148, 146, 142, 138, 134, 132, 127, 125, 121, 119, 115, 113, ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 90 W/R R/W 75 READY DSACK User’s Manual Function O Write/Read (Intel bus mode) This signal distinguishes write from read operations. O Read/Write (Motorola bus mode) This ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 76 BERR 74 B16 User’s Manual Function I Bus Error (Intel and Motorola bus mode) This active low signal informs the MUNICH32 that a bus cycle error ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 82 HOLD BR 79 HLDA BG 81 BGACK PM User’s Manual Function O Bus Hold Request (Intel bus mode) This signal is driven high when the MUNICH32 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 80 HLDAO BGO 66 AR User’s Manual Function O Bus Hold Acknowledge Passing ON (Intel bus mode) If another MUNICH32 has initiated a HOLD REQUEST the HOLD ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 40 INT/INT 44 RCLK 45 RSP 46 RDATA 61 SCLK User’s Manual Function O Interrupt Request An interrupt is given when a transmission/ reception error is detected, ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 51 … 47 CI(4:0) 56 … 53 JTEST (3:0) 65 TEST 67 TDATA 68 TSP 69 TCLK User’s Manual Function I Chip Identification Up to four MUNICH32 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-MQFP-160-1 Output (O) 60 RESET 41, 42, 43, 52, N.C. 70, 71, 72 User’s Manual Function I Reset - No Connect These pins are reserved and should not be connected ...
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Logic Symbol BE (3: (31:0) W/R R/W ADS/AS DS/PCHK Microprocessor Bus READY/DSACK Interface BERR B16 HOLD/BR HLDA/BG BGACK/PM HLDAO/BGO AR INT/INT 1) A31/DP3, A30/DP2, A29/DP1, A28/DP0, A[27:2] Figure 2 MUNICH32 Logic Symbol User’s Manual PEB ...
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Functional Block Diagram TCLK TSP TDATA TEST CD Serial Interface/Formatter Controller Unit TF Transmit Formatter TB Transmit Buffer MI Microprocessor Bus Interface 32 BE (3:0) A (31:2) D (31:0) ADS DS / W/R R/W AS Figure 3 Block Diagram ...
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The internal functions of MUNICH32 are partitioned into 8 major blocks. 1. Serial Interface, Formatter Control Unit CD – Parallel-Serial conversion, PCM timing, switching of the test loops, controlling of the multiplex procedure. 2. Transmit Formatter TF – HDLC frame, ...
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System Integration The MUNICH32 is designed to handle data channels of a PCM highway. It transfers the data between the PCM highway and a memory shared with a host processor via a 32-bit P interface. At ...
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PCM Highway (2.048 Mbit/s, 1.544 Mbit/s, 1.536 Mbit/s, 4.096 Mbit/s) MUNICH32 Figure 5 General System Interface (Intel Bus Mode) PCM Highway MUNICH32 MUNICH32 System Bus Optional Figure 6 General System Interface (Motorola Bus Mode) User’s Manual MUNICH32 ...
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MUNICH32’s bus interface consists bit bidirectional data bus (D31 … D0), 32/28 Address lines (A31 … A2, BE3 … BE0) or (A27 … A2, BE3 … BE0), four data byte parity lines DP(3:0), five lines (W/R/R/W, ADS/AS, ...
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PCM Highway R EPIC PEB 2056 INT/INT AR Local CPU Bus MUNICH32 PEB 20320 PCM System Interface CPU Bus Arbitration Figure 8 Architecture of a Central D-Channel Handler User’s Manual Signaling Highway Interrupt System HSCX Controller SAB 82525 Memory System ...
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T1/S2 Line Line Interface FALC54 PEB 2254 INT/INT AR MUNICH32 PEB 20320 PCM System Interface CPU Bus Arbitration Figure 9 Architecture of a Packet Switch/Router User’s Manual V.24, V.21, V.35, ... Line Driver Interrupt ESCC8 Controller SAB 82538 Memory System ...
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FALC54 PEB 2254 PCM System Interface INT/INT Local CPU Bus MUNICH32 PEB 20320 CPU Bus Arbitration Figure 10 MUNICH32 in a System with a RISC CPU Note: To reduce complexity the host interface is not explicitly shown here. User’s Manual ...
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T1/S2 Line Line Interface FALC54 PEB 2254 PCM System Interface INT/INT AR Local CPU Bus MUNICH32 PEB 20320 CPU Bus Arbitration Figure 11 MUNICH32 in a System using Multiport Memory Note: To reduce complexity the host interface is not explicitly ...
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Functional Description 2.1 Serial Interface The serial interface of MUNICH32 includes a data receive (RDATA) and a data transmit line (TDATA) as well as the accompanying control signals (RCLK = Receive Clock, RSP = Receive Synchronization Pulse, TCLK = ...
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SLOT PCM - Frame SLOT TCLK TSP TDATA FILL/MASK T1/DS1 - Mode Transmit Frame Timing ...
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SLOT PCM - Frame SLOT TCLK TSP TDATA FILL/MASK T1/DS1 - Mode Transmit Frame Timing SLOT 23 ...
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SLOT PCM - Frame SLOT TCLK TSP TDATA FILL/MASK CEPT - Mode Transmit Frame Timing SLOT 31 ...
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SLOT TSP RSP 4.096 Mbit/s PCM-format: even numbered slot allocation SLOT TSP RSP 4.096 Mbit/s PCM-format: odd numbered slot allocation ...
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Figure 16 Example: ...
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Microprocessor Interface A 64-channel DMA controller (32 channels in receive direction and 32 channels in transmit direction) with buffer chaining capability is integrated in the MUNICH32. It provides DMA functions for full duplex channels and allows ...
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Intel Mode The Intel mode has two submodes – parity mode (even parity) and non parity mode – chosen by strapping PM to ‘1’ or ‘0’ respectively. In Intel mode the lower (higher) ordered byte of a ...
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If the HOLD ACKNOWLEDGE is driven low while the MUNICH32 is performing a bus cycle, the bus is released later than two clock periods after de-assertion of HOLD ACKNOWLEDGE. The current bus cycle is finished with a bus cycle error. ...
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WRITE SCLK A31-A2 BE(3:0) [A27-A2] W/R ADS READY BERR [DP3-DP0], D(31:0) INT [PCHK] Figure 19 Write Cycle Timing Diagram (Intel mode) User’s Manual PEB 20320 Functional Description WRITE BERR Tristate 41 ITD03502 01.2000 ...
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MUNICH32 gets the Bus SCLK Tristate HOLD (extern) Tristate HOLD (intern) HLDA HLDAO Bus Cycle Max. 4 Clock Periods Figure 20 Bus Management for Intel Bus Mode Note 1: Bus Cycle means, that the MUNICH32 under consideration starts a read ...
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Motorola Mode In Motorola mode the bus is used in an asynchronous manner. The bus operation uses the handshake lines (AS, DS, DSACK and BERR) to control data transfer as shown in Figure 21, Figure 22. Address strobe AS ...
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READ SCLK A31-A2, BE (3:0) R DSACK D (31:0) BERR Figure 21 Read Bus Cycle Timing Diagram for Motorola Bus Mode WRITE SCLK A31-A2, BE (3:0) R DSACK D (31:0) BERR INT Figure 22 Write Bus ...
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MUNICH32 gets the Bus Max. 4 Clock Periods SCLK BR (extern) BR (intern) BG BGACK (extern) BGACK (intern) BGO Figure 23 Bus Management for Motorola Mode Note the Bus Management example it is assumed that the MUNICH32 under ...
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DMA Priorities Prioritization of Queueing DMA Cycles Priority Interrupt Highest priority Receive link list including accesses to the descriptors Transmit link list including accesses to the descriptors Lowest priority Configuration of a channel (action requests) The MUNICH32 will perform ...
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Basic Functional Principles MUNICH32 is a Multichannel Network Interface Controller for HDLC, offering a variety of additional features like subchanneling, data channels comprising of one or more time slots, DMI transparent or V.110/X.30 transmission and programmable ...
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RDATA Bit 0 Bit 1 RCLK Active Receive Channel (external) SCLK Active Receive X 0 Channel (internal) Load CD, CSR Data Protocol Operation for X into RD Phase of RD Protocol might write ...
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TDATA Bit 7 Bit 0 TCLK Active Transmit Channel (external) SCLK Active Transmit X 0 Channel (internal) Load CSR Data Protocol Operation for X into TF Phase of TF Protocol might write new Operation disabled Channel Config ...
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For example: a) 2.048-Mbit/s PCM highway 32 64-Kbit/s data channels (8 bits are sent with each PCM frame). Two long words of the buffer are allocated to each data channel 2.048-Kbit/s data channel The maximum buffer size for ...
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The receive buffer (RB FIFO buffer and also has a size of 64 long words, which allows storing the data of eight complete PCM frames before transferring to the shared memory. Figure 27 Partitioning of RB The data ...
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Receive Receive Interrupt DATA DATA Queue Receive Receive Receive Descriptor Descriptor Descriptor Transmit Transmit Transmit DATA DATA Descriptor Transmit Transmit Descriptor Descriptor Receive Receive Interrupt DATA DATA Queue Receive Receive Receive Descriptor Descriptor Descriptor Transmit Transmit Transmit DATA DATA Descriptor ...
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The shared memory allocated for each transmit and receive channel is organized as a chaining list of buffers set up by the host. Each chaining list is composed of descriptors and data sections. The descriptor contains the pointer to the ...
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The following Sections give Examples of Typical Transmit Situations for the Individual Modes Variable Size Frame Oriented Protocols (HDLC, TMB, TMR) Normal operation, handling of frame end (FE) indication and hold (H) indication. Note: 1. FNUM0 must be set to ...
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Figure 29 User’s Manual PEB 20320 Functional Description 55 01.2000 ...
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Fixed Size Frame Oriented Protocols (V110/X.30) Normal operation change (indicated by the V.110-bit in the transmit descriptor) Example for TRV = ‘11’ Note: 1. FNUM must be 0 for all transmit descriptors. 2. The actual E-, S-, ...
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Figure 30 User’s Manual PEB 20320 Functional Description 57 01.2000 ...
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Fixed Size Frame Oriented Protocols (V.110/X.30) Handling of frame end (FE) indication Note: 1. FNUM must be ‘0’ for all transmit descriptors. 2. The frame ( DATA 2 the octet no. y, containing the last data bit of ...
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Figure 31 User’s Manual PEB 20320 Functional Description 59 01.2000 ...
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Fixed Size Frame Oriented Protocols (V110/X.30) Handling of hold (H) indication Figure 32 User’s Manual PEB 20320 Functional Description 60 01.2000 ...
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Time Slot Oriented Protocol (TMA) Normal operation, handling of frame end (FE) indication and hold (H) indication. Note: 1. FNUM must be set to zero for TMA and the programmed flag with ...
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Figure 33 User’s Manual PEB 20320 Functional Description 62 01.2000 ...
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An activated transmission hold (hold bit in descriptor) prevents the MUNICH32 from sending more data frame end has not occurred just before, the current frame will be aborted and an interrupt generated. Afterwards, the interframe time-fill bytes will ...
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AR TH=1 in the Channel Specification handed over from Flag , Data 2 Flag, C, Frame ( ..., Data FNUM2 ... Data 1 Data ...
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Fixed Size Frame Oriented Protocol (V.110/X.30) Reaction to a channel specification containing Normal operation t t Note: 1. The times and are statistical but typically only a few clock cycles The current frame processed, ...
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AR TH=1 in the t Channel 1 Specificaton handed over from ... (1) ... 00 Frame ( Data 1 ) 10-y Octets FE ... . . . . Data 1 ITD04454 Figure ...
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AR TH=1 in the Channel Specification handed over from Time-Slot Boundaries , Data 2 , Data 1 FE= FNUM0 ... Data 1 Data 2 TH=0 in the Channel Specification ...
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Variable Size Frame Oriented Modes (HDLC, TMB, TMR) Reaction to a channel specification containing Silencing of poll cycles for hold. Note pulse for an action specification leading should be issued after ...
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AR TH=1 in the Channel Specification handed over from ... ... Flag Flag, Frame ( ..., Data 1 ) FNUM0 . . . Poll No Poll H=1? FNUM0 ...
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Fixed Size Frame Oriented Protocol (V110/.30) Silencing of poll cycles Note: 1. The times t and t are statistical but typically only a few clock cycles The TH bit (as all channel commands) ...
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AR (1) (2) Frame ( Data 1 ) Frame ( Data 1 10-y Octets 10 Octets FE ... Data 1 Data 2 TH=1 TH=0 in the in the t t Channel Channel ...
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Time Slot Oriented Protocol (TMA) Reaction to a channel specification containing Note for TMA and the programmed flag for TMA and FNUM2 is ignored. The ...
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AR TH=1 in the Channel Specification handed over from ... ... ... , TC, Data FNUM0 Poll No Poll H=1? FE= FNUM0 H ...
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In receive direction the MUNICH32 reads a receive descriptor, calculates the data address, writes the current receive descriptor address into the CCS, and exchanges data between the on-chip receive buffer and the external memory. After the data section has been ...
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Monitoring functions are implemented in MUNICH32 to discover errors or condition changes, i.e. – Receive frame end – Receive frame abort by overflow of the receive buffer or hold condition or recognized ABORT flag – Frame overflow frame ...
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Detailed Protocol Description In the following sections the protocol support of the MUNICH32 is described in detail for transmit and receive direction separately. Each section starts with a discussion of the general features proceeds with protocol variants and options ...
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E Frame Zero Insertions y= max (FNUM - FE=1 FNUM Figure 40 x Note the biggest integer smaller than . -- - For FNUM – < ...
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Interrupts The possible interrupts for the mode in transmit direction are: HI: issued if the HI bit is detected in the transmit descriptor (not maskable) FI: issued if the FE bit is detected in the transmit descriptor (maskable by FIT ...
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Generate FI, HI-Int. 2000181A st 1 Desc A0010002 FE=1 HOLD=0 HI=1 NO=1 CSM=0 FNUM=2 FNUM=1 Time Increases FLAG DATA 1 1 ..... 01111110 01010101 00010100010111110 01111110 11111111 8 Zero Insertion FLAG 01111110 111110111110111110111110111110111110111110111110 ...
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No FCS is generated here as CSM is ‘1’ for the second and third transmit descriptor. The FCS is supposed to be the last 2 bytes to be transmitted in this case, their validity is not checked internally. 6. ...
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HDLC Receive Direction General Features In receive direction: 1. The starting and ending flag (7E and extracted change of the interframe time-fill is recognized and reported by an interrupt. 3. The zero insertions (a ‘0’-bit after five ‘1’s ...
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The receiver is always in one of two possible interframe time-fill states called F and O. The following diagram explains them. A change from and from reported by an IFC ...
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For frames not fulfilling check a) no data are transferred to the shared memory irrespective of CS. Only an interrupt with the bit FI, SF and (possibly) ERR is generated. For frames fulfilling check a) but not check b) ...
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ERR: issued if one of the following error conditions has occurred: – FCS was incorrect – the bit length was greater than MFL – the frame was stopped by 7F – the frame could only be partly stored because of ...
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FLAG ..... 01111110 0100 0011 1000 0101 1000 0000 1100 0000 1001 1100 0000 0001 10111100 0011 1101 0011 Abort Sequence 3 01111111 Generate HI-Int. 8800203D st 1 Desc 20080000 000C0000 40080000 C0031C00 31 0 DATA ...
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FLAG 01111110 0000 0000 0000 0011 (shared) FLAG 6 01111110 0000 0000 0000 0011 FLAG 01111110 Generate FI, HI-Int. 8800303D rd 3 Desc 31 0 200C0000 C0080000 31 DATA FCS ...
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DATA 4 0101 0101 1101 1110 1010 0101 1000 0000 0010 0111 2 Flags with shared 0 0111 1110 111 1110 0000 0000 0000 FLAG DATA 6 01111110 0101 0101 1101 1110 1010 0101 1000 0000 0010 0111 DATA Ignored ...
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LFD is issued and always accompanied by NOB. CRCO shouldn’t be interpreted for a LFD frame. 7. Here the ending flag of the second frame is the starting flag of the third frame. 8. After an abort sequence data ...
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Generate FI, ERR-Int. 8800123D th 4 Desc 000C0000 000C0000 C0041800 C0014000 31 0 CRCO, NOB Last Access of a NOB Frame should be Ignored Figure 48 Note: 1. Only the 7 leading bytes are reported (the last ...
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For CRC = 0 (CRC 16) the correct FCS e.g. zeros for DATA 4 would be 00001 0100 0101 1110 the 5 th descriptor would then be 31 Figure 49 For Intel interface the only difference is in the receive ...
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TMB Transmit Direction General Features In transmit direction: – The starting and ending flag (00 – The interframe time-fill between frames is generated automatically. Options The different options for this mode are: – The number of interframe time-fill characters as ...
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Generate HI-Interrupt 88002005 20020000 80000000 FLAG DATA 1 FLAG ..... Figure 51 Note: 1. Data is transmitted according to Q.921 ...
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TMB Receive Direction General Features 1. The starting and ending flag (00 fill is recognized and extracted. 2. The number of bits within a frame is checked to be divisible The number of bytes within a frame ...
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Interrupts The possible interrupts for the mode in receive direction are: HI: issued if HI bit is detected in the receive descriptor (not maskable). FI: issued if a received frame has been finished as discussed in 1b) of the protocol ...
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DATA 1 FLAG 1 00000000 10111001 10000000 non octet synchronous 4 FLAG 10111100 0000000 10000000 DATA Ignored up to next Framestart 10100000 11110111 01010101 Generate FI-Int. 8800102A Desc 2 Desc 00040000 200C0000 C0020000 C0010000 ...
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Generate HI-Int. 8800202A th 4 Desc 20080000 00040000 40080000 C0000C00 31 0 DATA Last Access of a LFD Frame should be Ignored Figure 53 Note: 1. After Receive Initialization is detected ...
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For INV = 1 (channel inversion) all bits of the data stream (including DATA, FLAG) are interpreted inversely e.g. 1111 1111 0 would be interpreted as starting sequence then. For Intel interface the only difference is in the receive data ...
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TMR Transmit Direction General Features In transmit direction – the starting and ending flag (00 00 automatically. Options The different options for this mode are – the number of interframe time-fill characters as shown in Figure 29 by choosing FNUM ...
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Generate HI-Interrupt 88002005 20020000 80000000 FLAG DATA 1 FLAG ..... Frame of Effective 1 Length Byte Figure ...
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TMR Receive Direction General Features 1. The starting and the ending flag (00 00 characters of the starting flag and the last character of the ending flag is extracted. 2. The number of bits within a frame is checked to ...
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Options There are no options in receive direction for this mode. Interrupts The possible interrupts for the mode in receive direction are identical to those of TMB. Example: TMR channel with INV = 0 (no inversion) CRC = 1 (required) ...
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FLAG DATA 1 .... 00000000 00000000 10111001 10000000 DATA 3 10000000 00000000 10111100 11110101 DATA 4 11110011 11110111 11011101 11011011 11111111 Generate FI-Int. 88001035 Desc 2 Desc 00040000 200C0000 C0030000 C0020000 31 ...
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After receive initialization is detected all data are ignored until a starting sequence (16 ‘zeros’, ‘one’) is detected. 2. The octet synchronous (end) flag of one frame can be part of the (start) flag of the next frame. Note, ...
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TMA Transmit Direction General Features In the transmit direction – a slot-synchronous transparent data transmission – a high impedance overwrite for the masked bits in the slot – a programmable number of programmable fill characters between data (also slot synchronous) ...
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Example 1: (no subchanneling by fill/mask bits) TMA channel with TFLAG = B2 H INV = 0 (no data inversion) CRC = 0 (required) TRV = 00 (required (flag filtering) MODE = 00 (TMA) IFTF = 0 ...
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For INV = 1 the data stream would be inverted completely DATA 1 DATA 2 … Figure 59 For TFLAG has to be programmed to 00 DATA 1 DATA 2 D5 ...
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Example 2: (subchanneling by fill/mask bits) TMA channel with TFLAG = 00 (required for this case) H INV = 0 (no data inversion) CRC = 0 (required) TRV = 00 (required (required for subchanneling) MODE = 00 ...
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Figure 63 Note: Example 2 uses the same descriptors as example 1. Those bits in the data stream that are at places where fill/mask is ‘zero’ are overwritten by ‘Z’ i.e. high impedance. In all other protocols bits of the ...
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TMA Receive Direction General Features In the receive direction – a slot synchronous transparent data reception – a ‘1’ overwrite for masked bits in the slot – for FA = ‘1’ a slot synchronous programmable flag extraction is performed automatically. ...
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Slot Boundaries Octet Synchr 00040000 40040000 Figure 64 Note: The FE bit is never set in a receive descriptor. The ...
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For INV = 1 the receiver filters the inverse of the TFLAG as TC out of the data stream and inverts the data (only the octet synchronous 28 For Intel interface the data sections would ...
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Slot Boundaries Fill/Mask "one" Overwrite External Data 0 ...
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V.110/X.30 Transmit Direction General Features In transmit direction – the synchronization pattern for V.110/X.30 frame as shown in Table 1. – the framing for the different data rates with programmable E-, S-, X-bits – sending ‘0’ before all frames is ...
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Options The different options for this mode are: – the framing pattern, as shown in Table 2 to Table 5, is programmed by the bits TRV. Interrupts HI: issued if the HI bit is detected in the transmit descriptor (not ...
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Example X.30/V110 channel with (required) INV = 0 CRC = 0 TRV variable (all values shown in examples (required) MODE = 10 (V.110/X.30) Intel interface Channel No 00028000 20030000 ...
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TRV = ...
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TRV = ...
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TRV = ...
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V.110/X.30 Receive Direction General Features In receive direction – the starting sequence (00 followed by a ‘1’-bit) after initialization of H loss of synchronism is detected. – the synchronization pattern is monitored, after 3 consecutive erroneous frames a loss of ...
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Table 2 Framing for Networks with 600-bit/s Data Rate Intermediate Rate = 8 Kbit/s, i.e. Subchannelling with Only 1 Fill/Mask Bit Set Octet No ...
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Table 4 Framing for Networks with 2400-bit/s Data Rate Intermediate Rate = 8 Kbit/s, i.e. Subchannelling with Only 1 Fill/Mask Bit Set Octet No ...
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Options The different options for this mode are the framing pattern as shown in Table 2 to Table 5 is programmed by the bits TRV. Interrupts The possible interrupts for this mode are FRC: issued if the receiver has detected ...
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. . . ...
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...
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Desc 31 0 00080000 40042000 Loss of Synch. Figure 71 For Intel mode the data sections have the form Desc Figure 72 User’s Manual Functional Description 8FFF002D 8E5B002D 8F57002D 8C00002D 8E5B002D 8800022D ...
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Boundary Scan Unit In MUNICH32 a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and ...
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Table 6 Boundary Scan Sequence in PEB 20320 JTEST2 (TDI) Pin Pin I/O No. 1 Reset I 2 SCLK I 3 TEST TDATA O 6 TSP I 7 TCLK B16 ...
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Table 6 Boundary Scan Sequence in PEB 20320 (cont’d) JTEST2 (TDI) Pin D10 I/O 42 A10 O 43 D11 I/O 44 A11 O ...
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Table 6 Boundary Scan Sequence in PEB 20320 (cont’d) JTEST2 (TDI) Pin I/O 71 D25 I/O 72 A25 O 73 D26 I/O 74 A26 O 75 D27 I/O 76 A27 O 77 D28 I/O 78 A28/DP0 I/O 79 D29 I/O ...
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Table 7 Boundary Scan Test Modes Instruction (Bit 2 … 0) Test Mode 000 EXTEST (external testing) 001 INTEST (internal testing) 010 SAMPLE/PRELOAD (snap-shot testing) 011 IDCODE (reading ID code) 111 BYPASS (bypass operation) others handled like BYPASS EXTEST is ...
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Operational Description 3.1 Reset State Upon reset MUNICH32 is set to its initial state. The active high system reset clears the internal logic and causes MUNICH32 to tristate all output lines. Channel processing is deactivated. After reset all buffers ...
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Transmit Descriptor FNUM = 00 , i.e. shared flags in HDLC, only eight zero bits between sent frames for H TMB. The E-, S-, X-bits are all set to zero internally by the reset. The receiver is set into the ...
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CI4 CI3 Figure 74 CI4 CI3 CI2 CI1 CI0 Loc. of Ctrl. Start Addr ...
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Detailed Register Description 4.1 Organization of the Shared Memory Because the MUNICH32 reads only long words, all addresses of the link lists, interrupt queue and the CCS must be a multiple of four; i.e. the two least significant bits ...
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Receive Interrupt DATA Circular Channel 0 Queue Receive Descriptor Channel 0 Transmit Receive DATA Descriptor Channel 0 Channel 0 Transmit Transmit Descriptor Descriptor Channel 0 Channel 0 Figure 76 Organization of the Shared Memory User’s Manual PEB 20320 Detailed Register ...
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Control and Configuration Section Table 8 Buffer Size of the Control and Configuration Section Control and Configuration Section Action specification Interrupt queue specification Time slot assignment Channel specification Current descriptor address 4.2.1 Action Specification (Read Once After Each Action ...
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IN: Initialization procedure; setting this bit to one causes MUNICH32 to fetch all the time slot assignments and the channel specification of the selected channel (channel number). To avoid collision all time slots being reinitialized should deactivated ...
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Channelwise external loop One single logical channel is mirrored logically from serial data input to serial data output. The other channels are not affected by this operation. The data rate for this single logical channel has to be identical ...
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PCM MFL Initialization Procedure Read the complete time-slot assignment and the channel spec. ...
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Interrupt Queue Specification Interrupt Queue Address Interrupt Queue Address The interrupt queue is specified as ...
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Interrupt Information The next table shows the bit assignments for the interrupt information long word INT Interrupt Information When an interrupt occurs MUNICH32 sets the INT ...
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Action request interrupts ARACK: Action Request Acknowledge; MUNICH32 sets the ARACK bit to indicate that an action request has been serviced. ARF: Action Request Fail; MUNICH32 aborts an ACTION REQUEST, if the required configuration cannot be performed. An action ...
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Where ‘1’ means that the bit is always ‘1’ for this mode ‘0’ means that the bit is always ‘0’ for this mode ‘F’ means the bit is fixed by the version number ‘R’ means a bit that can only ...
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FE bit; ERR and FI are set if a transmit descriptor contains a HOLD bit no FE bit IFC: (HDLC mode, receive direction only) ...
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V.110/X.30 mode one of the following receive errors occurred: – data could only partly stored due to internal buffer overflow of RB – 3 consecutive frames had an error in the synchronization pattern (loss of synchronism) – a fast ...
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RB. 1.2 HDLC, TMB, TMR The MUNICH32 is unable to access the shared memory in time or has detected a bus cycle error (BERR = 0) ...
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General VN(3...1) Framing Bits Changed V.110/X30 mode received E, S, ...
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Time Slot Assignment (Read only once after each action request pulse with an action specification with set IN or RES bit) The time slot assignment provides the cross reference between the 32 (24) time slots of the PCM highway ...
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Channel Number: The channel number identifies the data channel. Its transmission mode is described in the respective channel specification. TTI: Transmit Time slot Inhibit; setting this bit to ‘1’ causes MUNICH32 to tristate the transmit time slot. The data is ...
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If an event leads to an interrupt with several bits set (e.g. FI and ERR) masking only a proper subset of them (e.g. ERR) will lead to an interrupt with the nonmasked bits set (e.g. FI). If all bits of ...
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CCS. For HDLC, TMB, TMR the rest of a frame which was only partially transferred before suspension of the receive descriptor is ...
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IFC bit after received bits. • For V.110/X.30: if the receiver was in the synchronized frame state it will go to the unsynchronized state after current ...
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For V.110/X.30 and TMA data bits might get lost. General Notes to Receive Commands: 1. After a pulse at the reset pin a channel having a time slot with ...
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For HDLC, TMB, TMR the first part of the frame of the suspended descriptor is sent and append by 011 1111 1111 111 for HDLC at least least 00 00 Afterwards the next frame is started. For ...
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(clears receive off condition, sets transmit abort condition, affects only the serial interface) This abort is performed in the transmit formatter at the serial interface. The currently transmitted ...
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(clears a previous transmit abort condition, affects the DMA interface and the serial interface) Before the MUNICH32 has got a transmit initialization command it will not transmit anything ...
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HDLC, V.110/X.30,TMB, TMR, TMA respectively and then set it into the transmit off condition. 4. Before changing the MODE, CRC, CS, TRV, INV, TFLAG bits or TTI or time slot ...
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Receive Frame Examples: a) 0x7E, data byte, 0x7E data byte copied to shared memory + frame end status SF-bit set no SF indication interrupt generated FI indication interrupt generated ERR interrupt generated due to wrong CRC’ b) 0x7E, data byte ...
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TRV: Transmission Rate of V.110/X.30. These signals determine the number of repeated D-bits in a V.110/X.30 frame. Table 9 TRV No. of Repetitions Note: In the other modes these bits must be ...
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FTDA: First Transmit Descriptor Address points to the beginning of the transmit data chaining list. This descriptor is only interpreted with a fast transmit abort or a transmit jump or a transmit initialization command read but ignored with ...
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Current Receive and Transmit Descriptor Address 31 Current Receive Descriptor Address Channel 0 Current Receive Descriptor Address Channel 31 Current Transmit Descriptor Address Channel 0 Current Transmit Descriptor Address Channel 31 For easier monitoring of the link lists the ...
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Transmit Descriptor HOLD HI Transmit Data Pointer Next Transmit Descriptor Pointer V.110 CSM Transmit Data Pointer Next Transmit Descriptor Pointer FE: Frame End; ...
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HOLD: If the MUNICH32 detects a hold bit it – generates an interrupt with ERR bit set V.110/X.30 mode – sends the data in the current transmit data section – generates the FCS bits for ...
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Intel Mode Motorola Mode ...
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FNUM = k means that after the current frame characters are sent ( times – 1) times times ...
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For example (Intel mode): 1) ADD = 01 byte 2 byte 1 byte 0 byte 6 byte 5 byte 4 byte 3 – 2) ADD = 00 byte 3 byte 2 byte ...
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Next Transmit This 32-bit pointer contains the start address of the next transmit Descriptor Pointer: descriptor. After sending the indicated number of data bytes, MUNICH32 branches to the next transmit descriptor to continue transmission. The transmit descriptor is read entirely ...
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Receive Descriptor HOLD Receive Data Pointer Next Receive Descriptor Pointer Status Receive Data Pointer Next Receive ...
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Afterwards the next received frame is transferred into the next receive descriptor. Interrupts are also generated again. • For V.110/X.30, TMA the device puts the next data into the next receive descriptor. Interrupts are also generated again. The HOLD ...
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HDLC, TMB, TMR if the end of a frame was stored in the receive data section status gives the receive status determined by RD (interrupt with set FI bit is generated) • for V.110/X.30 mode ...
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NI means the bit may be ‘1’ or ‘0’ but does not cause an interrupt with set ERR bit. ILN means that it may be ‘1’ or ‘0’ but should not be evaluated if LFD or NOB is also ‘1’. ...
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Note: In case of multiple errors all relevant bits are set. In case of ROF = 1 only the error conditions of the frame within which the overflow occurred are reported. Later frames that are aborted do not change the ...
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Application Notes 5.1 Test Loops 5.1.1 Test Loop Definitions for the MUNICH32 Two basic types of test loops are provided by the MUNICH32, internal and external. Each of these types is further subdivided into channelwise and complete test loops ...
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Internal Channelwise Test Loop One (and only one) logical channel is mirrored from the serial data output to the serial data input. The other logical channels are not affected by this operation. The transmit and receive data rates for ...
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CD Enable Ext. Complete Loop P Interface Figure 83 5.1.1.4 External Channelwise Test Loop One (and only one) logical channel is mirrored from the serial data input to the serial data output. The other logical channels are not affected by ...
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Test Loop Activation All of the test loops are closed (activated) and opened (deactivated) by setting/resetting the appropriate combination of bits in the Action Specification (Table 10). Any unlisted combination of LOC, LOOP and LOOPI is an invalid operation. ...
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Software Operations Close and open internal complete loop. Close and open internal channelwise loop. Close and open external complete loop. Close and open external channelwise loop. Change from internal complete loop to internal channelwise loop. Change from external complete ...
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Test Loop Examples 5.1.4.1 Internal Channelwise Test Loop Generate HW RESET, and hold off RSP/TSP for 1000 SCLK cycles. ASP: A104-8004 IQS: ICQ 0000-001F TSA[0]: 00FF-00FF TSA[1…31]: 0000-0000 ( 31) CSP[0]: 00E9-0006 FRDA FTDA 0000-0002 CSP[1…31] 0000-0000 CRA[0…31] 0000-0000 ...
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Generate AR Pulse and wait for INT signal (set up TS0 and CH0). Read interrupt queue: ICQ: 9000-8000 9000-1000 Set ASP for Internal Channelwise Loop test ASP: A104-0028 Generate AR Pulse and wait for INT signal. Read interrupt queue: ICQ: ...
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External Channelwise Test Loop Generate HW RESET, and hold off RSP/TSP for 1000 SCLK cycles. ASP: A104-8004 IQS: ICQ 0000-001F TSA[0]: 00FF-00FF TSA[1…31]: 0000-0000 ( 31) CSP[0]: 00E9-0006 FRDA FTDA 0000-0002 CSP[1…31] 0000-0000 CRA[0…31] 0000-0000 ( 32) CTA[0…31] 0000-0000 ...
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Generate AR Pulse and wait for INT signal (set up TS0 and CH0). Read interrupt queue: ICQ: 9000-8000 9000-1000 9000-1000 Set ASP for External Channelwise test loop ASP: A104-0030 Generate AR Pulse and wait for INT signal. Read interrupt queue: ...
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... It is suggested that the reader has some knowledge about the MUNICH32 before reading this application note. Detailed information about the MUNICH32, its features and memory structures are given in the MUNICH32 PEB20320 Data Sheet. User’s Manual PEB 20320 ...
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Hardware The processor system is based on a Motorola 68040 processor. It contains 512 KByte SRAM, a bus controller and peripherals like timer, EPROM and interrupt controller. The application specific hardware is integrated by using a Peripheral Connector and ...
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Application Specific Hardware The application specific hardware consists of an ISDN primary rate interface and an Ethernet interface. The MUNICH32 PEB 20320 in conjunction with the layer 1 SIEMENS components ACFA (Advanced CMOS Frame Aligner) PEB 2035 and PRACT (Primary ...
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System Architecture The system architecture is shown in Figure 88. The MUNICH32, the CPU and the LAN controller store data in the shared memory. The communication between CPU and alternate bus master is done via the shared memory. The CPU ...
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Bus Arbitration Since three devices are using the bus it is necessary to implement a bus arbitration. Each bus master requests bus mastership and awaits bus control given the arbiter. The bus arbitration protocol is also Motorola ...
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Bus Timing Adaptation The bus controller manages memory accesses of all bus masters (CPU, MUNICH32 or LAN controller). The bus controller timing is Motorola 68040 specific. The MUNICH32 bus interface is either Intel specific or Motorola 68020/030 specific. Therefore ...
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The LAN controller’s (i82596) bus timing also needs to be adapted. The address lines A1, AO, Size 0 and Size 1 need to be generated, because the LAN controller performs 8 bit and 16 bit cycles as well as 32 ...
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DDS Tasks The message transfer between the modules is the main task of the DDS, realized by some service routines. DDMs and APMs are integrated in the DDS by executing a Module Init Routine. The Module Init Routine is called ...
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Message Descriptor Pool MUNICH32/LAN Controller Descriptor Pool Figure 92 Memory Management User’s Manual PEB 20320 Application Notes Allocate Free Allocate Free 190 ITS08290 01.2000 ...
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Device Driver Module MUNICH32 Tasks The MUNICH32 Device Driver Module has to prepare all memory structures for the MUNICH32. The ACTION REQUEST Pulse has to be generated. The device driver module also has to treat the MUNICH32 interrupts. Message ...
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Function Action TxShutDown Initialize Channel Only bit is set, gives ‘transmit off’ command or ‘transmit abort’ command, ACTION REQUEST Pulse is generated. RcJump Initialize Channel Only bit is set, If last command was ‘transmit off’ or ‘transmit abort’ ‘transmit clear’ ...
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Programming the MUNICH32 for this Application The basic programming of the MUNICH32 for this application is realized in the Module Initialization Routine. Further programming is done by calling the function ‘Init Channel’ for each channel once. Transmit data is then ...
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Send Frame Routine Calling ‘SendFrame’ after initialization of a channel results in executing ‘AddHdlcFrame’. In that routine the transmit descriptors are disconnected from the message and linked to the memory structures. If the message source is the ‘MROUTE Application Module’ ...
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ISDN 64 kbit/s each Channel fe = SET Frame Descr 0 Ch1 Count Count EOF = SET Frame Descr Count Count EOF 1 = Figure 93 Insertion of additional Information To make efficient use ...
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The fe-bit marks the end of one HDLC frame, the EOF bit marks the end of the Ethernet frame. The additional information comprises the 8-bit word descriptor count, 16-bit word frame count and EOF a 8-bit variable which indicates the ...
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Performance Considerations Some considerations about the performance are made by investigating the maximum data rate. Further investigations are made about the bus occupancy by all busmasters and the MUNICH32 poll access’ influence on the data rate. Finally the processing ...
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Bus Occupancy The bus occupancy during normal operation is shown in Figure 96. In this case the data buffer size was 32 Byte. The CPU has busmastership during 90% of the time. The MUNICH32 as well as the LAN controller, ...
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MUNICH32 Polling The influence of the polling can be illustrated by showing the bus occupancy of MUNICH32 poll accesses only. M32 17 % Figure 97 Bus Occupancy During Polling Here the MUNICH32 is polling 31 channels (= 31 Every access ...
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Frame Processing During normal operation the processing of a frame comprises three consecutive parts. During transmission from ISDN to LAN the frame is first processed from the MUNICH32, then from the CPU and finally from the LAN controller. MUNICH32 CPU ...