peb20320 Infineon Technologies Corporation, peb20320 Datasheet - Page 53

• Manufacturer Part Number: peb20320
• Description: Multichannel Network Interface Controller For Hdlc
• Manufacturer: Infineon Technologies Corporation

The shared memory allocated for each transmit and receive channel is organized as a
chaining list of buffers set up by the host. Each chaining list is composed of descriptors
and data sections. The descriptor contains the pointer to the next descriptor, the start
address and the size of a data section. It also includes control information like frame end
indication, transmission hold and rate adaption with interframe time-fill.
In the transmit direction the MUNICH32 reads a transmit descriptor, calculates the data
address, writes the current transmit descriptor address into the CCS, and fills the on-chip
transmit buffer. When the data transfer of the specified section is completed, the
MUNICH32 releases the buffer, and branches to the next transmit descriptor. If a frame
end is indicated the HDLC, TMB or TMR frame will be terminated and a specified number
of the interframe time-fill byte will be sent in order to perform rate adaption. If frame end
is found in a transmit descriptor TMA channel the specified number of programmable
TMA flags is appended to the data in the descriptor. If frame end is found in a transmit
descriptor of a V.110/X.30 channel the frame is aborted (after the data in the descriptor
are sent) by finishing the current 10-octet frame with ‘zeros’ and sending 2 more 10-octet
frames with ‘zeros’ which leads to a loss of synchronism on the peer side. An adjustment
for the inserted zeros in HDLC is programmable, which leads to a reduction of the
specified number of interframe time-fill by
be used to send long HDLC frames with a more or less fixed data rate in spite of the zero
insertions. A maskable interrupt is generated before transmission is started again.
User’s Manual
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of the number of zero insertions. This can
Functional Description
PEB 20320
01.2000