is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 19

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Device Initialization At Power-On
(Power-On Sequence)
As is the case with conventional DRAMs, the IS42S16128
product must be initialized by executing a stipulated
power-on sequence after power is applied.
After power is applied and V
stipulated voltages, set and hold the CKE and DQM pins
HIGH for 100 µs. Then, execute the precharge command
to precharge both bank. Next, execute the auto-refresh
command twice or more and define the device operation
mode by executing a mode register set command.
The mode register set command can be also set before
auto-refresh command.
Mode Register Settings
The mode register set command sets the mode register.
When this command is executed, pins A0 to A7, A8, and
A9 function as data input pins for setting the register, and
this data becomes the device internal OP code. This OP
code has four fields as listed in the table below.
Note that the mode register set command can be ex-
ecuted only when both banks are in the idle (inactive)
state. Wait at least two cycles after executing a mode
register set command before executing the next com-
mand.
CAS Latency
During a read operation, the between the execution of the
read command and data output is stipulated as the CAS
latency. This period can be set using the mode register
set command. The optimal CAS latency is determined by
the clock frequency and device speed grade. See the
"Operating Frequency / Latency Relationships" item for
details on the relationship between the clock frequency
and the CAS latency. See the table on the next page for
details on setting the mode register.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
A9, A8, A7
A6, A5, A4
A2, A1, A0
Input Pin
A3
CAS Latency
Burst Length
Write Mode
Burst Type
CC
Field
and V
CC
Q reach their
Burst Length
When writing or reading, data can be input or output data
continuously. In these operations, an address is input only
once and that address is taken as the starting address
internally by the device. The device then automatically
generates the following address. The burst length field in
the mode register stipulates the number of data items
input or output in sequence. In the IS42S16128 product,
a burst length of 1, 2, 4, 8, or full page can be specified.
See the table on the next page for details on setting the
mode register.
Burst Type
The burst data order during a read or write operation is
stipulated by the burst type, which can be set by the mode
register set command. The IS42S16128 product supports
sequential mode and interleaved mode burst type set-
tings. See the table on the next page for details on setting
the mode register. See the "Burst Length and Column
Address Sequence" item for details on I/O data orders in
these modes.
Write Mode
Burst write or single write mode is selected by the OP code
(A9, A8, A7) of the mode register.
A burst write operation is enabled by setting the OP code
(A9, A8, A7) to (0,0,0). A burst write starts on the same
cycle as a write command set. The write start address is
specified by the column address and bank select address
at the write command set cycle.
A single write operation is enabled by setting OP code
(A9, A8, A7) to (1,0,0). In a single write operation, data is
only written to the column address and bank select
address specified by the write command set cycle without
regard to the bust length setting.
ISSI
19
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