is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 25

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read com-
mand is output in place of the data due to the previous
read command.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the data
for the previous write command.
CAS latency = 2, burst length = 4
CAS latency = 2, burst length = 4
COMMAND
COMMAND
CLK
I/O
CLK
I/O
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
D
t
CCD
IN
t
CCD
B0
D
OUT
D
IN
A0
B1
D
OUT
D
IN
B0
The interval between two read command (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
B2
D
OUT
D
IN
B1
B3
D
OUT
B2
D
OUT
B3
ISSI
CCD
CCD
) must be
) must be
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