is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 31

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Write Cycle (Full Page) Interruption
Using the Burst Stop Command
The IS42S16128 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IS42S16128 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continu-
ing with a+1, a+2, a+3, etc. A burst stop command must
Burst Data Interruption Using the
U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless
of the CAS latency, two clock cycles (t
U/LDQM pins goes HIGH, the corresponding outputs go
to the HIGH impedance state. Subsequently, the outputs
are maintained in the high impedance state as long as
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
CAS latency = 2, 3, burst length = full page
CAS latency = 2, burst length = 4
COMMAND
COMMAND
I/O8-I/O15
I/O0-I/O 7
UDQM
LDQM
CLK
CLK
I/O
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
WRITE A0
D
READ A0
IN
A0
DATA MASK (UPPER BYTE)
QMD
D
IN
) after one of the
A1
t
DATA MASK (LOWER BYTE)
QMD=2
D
D
D
OUT
OUT
IN
A
A0
A0
D
D
IN
OUT
A1
be executed to terminate this cycle. A precharge com-
mand must be executed within the ACT to PRE command
period (t
After the period (t
following the execution of the burst stop command has
elapsed, the write cycle terminates. This period (t
zero clock cycles, regardless of the CAS latency.
that U/LDQM pin remains HIGH. When the U/LDQM pin
goes LOW, output is resumed at a time t
output control operates independently on a byte basis
with the UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte
output (pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
HI-Z
A1
D
D
IN
RAS
OUT
HI-Z
A2
max.) following the burst stop command.
A2
BURST STOP
WBD
D
BST
INVALID DATA
OUT
) required for burst data input to stop
t
WBD=0
A3
PRECHARGE (BANK 0)
PRE 0
HI-Z
Don’t Care
t
RP
ISSI
QMD
later. This
WBD
) is
31
®