is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 26

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed
in the HIGH impedance state at least one cycle before
data is output during this operation.
26
IS42S16128
CAS latency = 2, burst length = 4
CAS latency = 3, burst length = 4
COMMAND
COMMAND
CLK
CLK
I/O
I/O
WRITE (CA=A, BANK 0)
WRITE (CA=A, BANK 0)
D
D
WRITE A0
WRITE A0
IN
IN
A0
A0
READ B0
READ B0
t
t
CCD
CCD
READ (CA=B, BANK 0)
READ (CA=B, BANK 0)
HI-Z
D
OUT
HI-Z
B0
D
D
OUT
OUT
The interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
B0
B1
Integrated Silicon Solution, Inc. — 1-800-379-4774
D
D
OUT
OUT
B2
B1
CCD
D
D
OUT
OUT
) between command must be at least
B2
B3
D
OUT
B3
Don’t Care
ISSI
03/13/00
Rev. A
®