is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 27

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding to
the new write command can be input at the point new write
command is executed. To prevent collision between
input and output data at the I/On pins during this opera-
tion, the
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
CAS latency = 2, 3, burst length = 4
COMMAND
U/LDQM
CLK
I/O
READ (CA=A, BANK 0)
READ A0
HI-Z
D
WRITE B0
IN
t
CCD
B0
WRITE (CA=B, BANK 0)
D
IN
B1
D
IN
B2
output data must be masked using the U/LDQM pins. The
interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
IN
B3
CCD
) between these commands must be at least
ISSI
27
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