hip6503 Intersil Corporation, hip6503 Datasheet
hip6503
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hip6503 Summary of contents
Page 1
... DUAL HIP6503CB HIP6503CBZ (Note) linear regulators HIP6503CBZ-T (Note SOIC Tape and Reel HIP6503EVAL1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Block Diagram 12V 12V MONITOR 10.8V/9.8V 1V8IN EA3 + - TO UV DETECTOR 1V8SB TO 5VSB 40µA FAULT/MSEL UV DETECTOR UV COMP 4.15V 5VDL GND 5V 3V3DLSB 3V3DL 3V3 EA4 - + 4.4V/3.4V 3V3 MONITOR 5V MONITOR 2.97V/2.8V 4.5V/4.25V MONITOR ...
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... C DUAL SB OUT3 FAULT SLP_S3 SLP_S5 EN5VDL SHUTDOWN 3 HIP6503 LINEAR REGULATOR CONTROLLER LINEAR CONTROLLER REGULATOR HIP6503 FIGURE 2. 12V 3V3 1V8SB 5V 1V8IN 3V3DLSB Q3 3V3DL HIP6503 FAULT/MSEL R SEL S3 S5 EN5VDL GND FIGURE 3. Q1 LINEAR V MEM 2.5V/3.3V V CLK LINEAR 2.5V CONTROL Q5 LOGIC 5VSB Q1 DRV2 VSEN2 C OUT2 ...
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... Regulation (Note 2) VSEN2 Nominal Voltage Level VSEN2 Nominal Voltage Level VSEN2 Undervoltage Rising Threshold VSEN2 Undervoltage Hysteresis (Note 3) VSEN2 Output Current 4 HIP6503 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package (Note +0.3V Maximum Junction Temperature (Plastic Package 150°C 12V Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s 300° ...
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... FAULT Output Impedance TEMPERATURE MONITOR Fault-Level Threshold (Note 6) Shutdown-Level Threshold (Note 6) NOTES: 2. Sleep-State Only for 3.3V Setting 3. Parameters not guaranteed for 5VSB < 4.0V Ambient Temperatures Less Than 50°C. 5. Guaranteed by Correlation. 6. Guaranteed by Design. 5 HIP6503 SYMBOL TEST CONDITIONS I 5VSB = 5V 1kΩ DRV2 SEL R = 10kΩ SEL ...
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... In case of an undervoltage on any of the controlled outputs, on any of the monitored ATX supplies case HIP6503 overtemperature event, this pin is used to report the fault condition by being pulled to 5VSB. SS (Pin 16) Connect this pin to a small ceramic capacitor (no less than 5nF ...
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... This pin is the output of the internal 1.8V regulator (V This internal regulator operates for as long as 5VSB is applied to the HIP6503. This pin is monitored for under- voltage events. 1V8IN (Pin 2) This pin is the input supply for the 1.8V internal regulator’s pass element. Connect this pin to the 3.3V output ...
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... Additionally, the S3 pin features a 200µs delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200µs interval, if the S5 pin is low, the HIP6503 switches into S5 sleep state; if the S5 pin is high, the HIP6503 goes into S3 sleep state. 5VSB ...
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... SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6503 will assume active state wake-up and keep off the required outputs until some time (typically 25ms) after the ATX’s main outputs used by the application (3.3V, 5V, and 12V) exceed the set thresholds ...
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... Pulling the SS pin low effectively shuts down all the pass elements. Upon release of the SS pin, the HIP6503 undergoes a new soft-start cycle and resumes normal operation in accordance to the ATX supply and control pins status ...
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... Ideally, the power 11 HIP6503 plane should support both the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers to create power islands connecting the filtering components (output capacitors) and the loads ...
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... If the ATX supply does not meet the specifications, certain imbalances between the ATX’s outputs and the HIP6503’s regulation levels could have as a result a brisk transfer of energy from the input capacitors to the supplied outputs. At the transition between active and ...
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... U1 3V3DL 5 HIP6503 C10 1V8IN 330µF 2 FAULT/MSEL EN5VDL C15 GND 0.1µF FIGURE 12. TYPICAL HIP6503 APPLICATION DIAGRAM + C2 1000µF C4 1µF 1 DRV2 Q1 19 2SC5001 VSEN2 330µF 1µF VCLK 6 C11 + C12 150µF 1µF 5VDLSB ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 HIP6503 M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...