hip6503 Intersil Corporation, hip6503 Datasheet - Page 8

• Manufacturer Part Number: hip6503
• Description: Multiple Linear Power Controller With Acpi Control Interface
• Manufacturer: Intersil Corporation

Not shown in these diagrams is the deglitching feature used
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2µs filter (typically 1 -
4µs). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200µs delay in
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200µs interval, if
the S5 pin is low, the HIP6503 switches into S5 sleep state; if
the S5 pin is high, the HIP6503 goes into S3 sleep state.
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10µA current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
FIGURE 6. 2.5V
INTERNAL
3V3DLSB
DEVICES
5VDLSB
FIGURE 5. 5V
5V, 12V
VSEN 2
5V, 12V
3V3DL
VSEN2
VSEN1
5VSB
5VDL
VCLK
5VSB
DRV2
3.3V,
DLA
3.3V,
DLA
S3
S5
S3
S5
3V
MEM
DUAL
DUAL
, 3.3V
/3V
TIMING DIAGRAM FOR EN5VDL = 0;
SB
MEM
, AND 2.5V
8
CLK
TIMING DIAGRAM
HIP6503
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figure 7 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10µA current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the
3.3V
inputs start their transition, resulting in the output voltages
ramping up proportionally. The ramp-up continues until time
T3 when the two voltages reach the set value. As the soft-
start capacitor voltage reaches approximately 2.75V, the
under-voltage monitoring circuit of this output is activated
and the soft-start capacitor is quickly discharged to
approximately 1.25V. Following the 3ms (typical) time-out
between T3 and T4, the MSEL and EN5VDL selections are
latched in, and the soft-start capacitor commences a second
ramp-up designed to smoothly bring up the remainder of the
voltages required by the system. At time T5 all voltages are
within regulation limits, and as the SS voltage reaches
2.75V, all the remaining UV monitors are activated and the
SS capacitor is quickly discharged to 1.25V, where it
remains until the next transition. As the 2.5V
only active while in an active state, it does not come up, but
0V
0V
FIGURE 7. SOFT-START INTERVAL IN A SLEEP STATE
DUAL
T0
VOLTAGES
OUTPUT
(1V/DIV)
T1 T2
/3.3V
V
V
(1V/DIV)
(ALL OUTPUTS ENABLED)
OUT3
OUT1
5VSB
SB
and 1.8V
(3.3V
(1.8V
T3
DUAL
SB
SOFT-START
)
(1V/DIV)
/3.3V
SB
TIME
T4
error amplifiers’ reference
SB
)
T5
V
(2.5V
OUT5
V
OUT2
MEM
CLK
(5V
)
DUAL
output is
(2.5V
V
July 21, 2005
OUT4
)
FN4882.5
CLK
)