hip6503 Intersil Corporation, hip6503 Datasheet - Page 10

• Manufacturer Part Number: hip6503
• Description: Multiple Linear Power Controller With Acpi Control Interface
• Manufacturer: Intersil Corporation

In HIP6503 applications, loss of any one active ATX output
(3.3V
monitors) during active state operation causes the chip to
switch to S5 sleep state, in addition to reporting the input UV
condition on the FAULT/MSEL pin. Exiting from this forced-
S5 state can only be achieved by returning the faulting input
voltage above its UV threshold, by resetting the chip through
removal of 5V
potential lower than 0.8V.
Output Voltages
The output voltages are internally set and do not require any
external components. Selection of the V
voltage is done by means of an external resistor connected
between the FAULT/MSEL pin and ground. An internal 40µA
(typical) current source creates a voltage drop across this
resistor. Following every 3.3V
Soft-Start Circuit), this voltage is compared with an internal
reference and the setting is latched in. Based on this
comparison, the output voltage is set at either 2.5V
(R
that no capacitor is connected to the FAULT/MSEL pin; the
presence of a capacitive element at this pin can lead to false
memory voltage selection. See Figure 9 for details.
Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slew-
up speed of the output voltages controlled by the HIP6503,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
SEL
FIGURE 9. 2.5/3.3V
R
10kΩ
1kΩ
SEL
IN
= 1kΩ), or 3.3V (R
, 5V
R
SEL
FAULT/MSEL
IN
V
2.5V
3.3V
, or 12V
MEM
CIRCUITRY DETAILS
SB
bias voltage, or by bringing the SS pin at a
MEM
IN
; as detected by the on-board voltage
SEL
OUTPUT VOLTAGE SELECTION
40µA
10
SB
= 10kΩ). It is very important
MEM VOLTAGE
SELECT COMP
ramp-up or chip reset (see
+
-
0.2V
5VSB
MEM
+
-
memory
HIP6503
current dedicated to charging the output capacitors can be
calculated with the following formula:
I
C
V
Σ
capacitance and the voltage of an output (total charge
delivered to all outputs)
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the HIP6503
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the HIP6503
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
Layout Considerations
The typical application employing a HIP6503 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical by-pass
current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible, but not excessively far from the clock chip or
the processor. Insure the 1V8SB, DRV2 and VSEN2
connections are properly sized to carry 250mA without
significant resistive losses; similar guideline applies to the
VCLK output, which can deliver as much as 800mA (typical).
As the current for the VCLK output is provided from the ATX
3.3V, the connection from the 3V3 pin to the 3.3V plane
should be sized to carry the maximum clock output current
while exhibiting negligible voltage losses. Similarly, the
5VSB and the 5V pins are carrying significant levels of
current - for best results, insure they are connected to their
respective sources through adequately sized traces. The
pass transistors should be placed on pads capable of
heatsinking matching the device’s power dissipation. Where
applicable, multiple via connections to a large internal plane
can significantly lower localized device temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
I
SS
COUT
BG
SS
(C
- soft-start current (typically 10µA)
OUT
- soft-start capacitor
- bandgap voltage (typically 1.26V)
=
x V
----------------------------- -
C
SS
OUT
I
SS
×
V
) - sum of the products between the
BG
×
Σ
(
C
OUT
×
V
OUT
)
, where
July 21, 2005
FN4882.5