tmp88f846ug TOSHIBA Semiconductor CORPORATION, tmp88f846ug Datasheet - Page 33

• Manufacturer Part Number: tmp88f846ug
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.1.5.3
2.1.5.4
2.1.5.5
2.1.5.6
2.1.5.7
SYSCR2<SYSCK> = 0, the system clock is turned off, causing the CPU to become locked up. To prevent
this problem, upon detecting SYSCR2<XEN> = 0, SYSCR2<XEN> = SYSCR2<SYSCK> = 0 or
SYSCR2<SYSCK> = 1, the device automatically generates an internal reset signal to let the system clock
continue oscillating.
defined threshold voltage.
for the power-on reset signal and voltage detecting signal. These bits are read from the flash memory and
latched internally during the power-on warming up period (tPOWUP). The trimming data reset is gener-
ated if the trimming data is corrupted due to noise or other causes.A supply voltage reset is generated
internally when the supply voltage (VDD) falls below the predefined threshold voltage.
Watchdog Timer Reset
System Clock Reset
Power-on Reset
Supply voltage reset
Triming data reset
Refer to the Section “Watchdog Timer.”
When SYSCR2<XEN> is cleared to 0 or when SYSCR2<XEN> is cleared to 0 while
A power-on reset is generated internally when the supply voltage (VDD) is turned on.
Refer to Section “Power on reset”.
A supply voltage reset is generated internally when the supply voltage (VDD) falls below the pre-
Refer to Section “Supply voltage reset”.
Trimming data bits are provided for adjusting the ladder resistor used to generate the reference voltages
• To prohibit the address trap:
1. Modify the iram (mapping attribute) area to (00040H to 000BFH) in the memory map win-
2. Set 000C0H to "address trap prohibition area" as a new eram (mapping attribute) area.
3. Load the user program
4. Execute the address trap prohibition code in the user’s program
dow.
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TMP88F846UG