lf3304 LOGIC Devices Incorporated, lf3304 Datasheet
lf3304
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lf3304 Summary of contents
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... MODE 1-0 RWB DESCRIPTION The LF3304 is a dual line buffer/FIFO, designed to operate at HDTV rates. The LF3304 will operate in two dis- tinct modes: Line Buffer and FIFO. In these modes the two memories can operate independently or with common control. The LF3304 comprises two 12-bit 4K ...
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... RWA — Reset Write A The write address pointer is reset to the first physical location when RWA is set LOW. After power up, the LF3304 requires a Reset Write for ini- tialization because the write address pointer is not defined at that time. RRA — Reset Read A The read address pointer is reset to the first physical location when RRA is set LOW ...
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... LF3304 on the rising edge of WCLKB when the device is config- ured for writing. RCLKB — Read Clock B Data is read from the LF3304 and pre- sented on the output port (BOUT after t has elapsed from the rising D edge of RCLKB when the device is configured for reading and the output port is enabled ...
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... DEVICES INCORPORATED LOW. Controls LDA — RAM Array A Load When LDA is LOW, data on AIN 11-0 is latched in the LF3304 on the rising edge of WCLKA. LDB — RAM Array B Load When LDB is LOW, data on BIN 11-0 is latched in the LF3304 on the rising edge of WCLKB. WENA — Write Enable A ...
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... PAEB register and has no default value. PAEB is synchronized to the rising edge of RCLKB. FIFO MODE OPERATION Initialization Upon power-up, the LF3304 requires the initialization of the internal read and write address pointers. This ini- tialization sequence can be done by either a Flag Enable Reset or a Flag Disable Reset. ...
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... Ground ≤ V ≤ V (Note 12 Ground ≤ V ≤ V (Note 12) OUT CC (Notes 5, 6) (Note 25° MHz 25° MHz A 6 LF3304 Dual Line Buffer/FIFO Voltage Supply 3.00V ≤ V ≤ 3.60V CC 3.00V ≤ V ≤ 3.60V CC Min Typ Max Unit 2.4 V 0.4 V 2.0 5 ...
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... Skew Time Between Read and Write Clocks for PAEx and PAFx SKEW2 *C - Available in Commercial Temperature Range ( Available in Industrial Temperature Range (- Notes 9, 10 (ns) PERATING ANGES C to +70 ° +85 ° 7 Dual Line Buffer/FIFO LF3304 - Available Speed and Temperature Min Max Min Max ...
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... PWL t CYC RENA t AC RENB AOUT 11–0 (n–2) (n–1) BOUT 11– SKEW1 WCLKA WCLKB RRA = RRB = HIGH OEA = OEB = LOW t t WES WEH (n+1) t RES t REH (n) (n+ REF REF 8 LF3304 Dual Line Buffer/FIFO (n+2) (n+ WFF WFF (n+2) (n+3) Video Imaging Products 9/28/2005–LDS.3304-I ...
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... ROGRAMMABLE LAG OAD WCLKA WCLKB AIN 11–0 PAEx BIN 11–0 ADDRA ADDRB t LDS LDA LDB WENA WENB (n+1) (n+ (n) (n+1) IMING PAFx t LDH 9 Dual Line Buffer/FIFO t RH (0) (1) (n+2) (0) (0) Video Imaging Products LF3304 (1) 9/28/2005–LDS.3304-I ...
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... LMOST MPTY WCLKA WCLKB PAEA PAEB RCLKA RCLKB UTPUT NABLE AND ISABLE OEA OEB AOUT 11–0 BOUT 11–0 F LAG t PAF F LAG t t PAE SKEW2 t OHZ 10 Dual Line Buffer/FIFO t PAF t SKEW2 t PAE t OLZ HIGH IMPEDANCE Video Imaging Products 9/28/2005–LDS.3304-I LF3304 ...
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... Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst- 11 LF3304 Dual Line Buffer/FIFO case operation of any device always provides data within that time. 11. For the t test, the transition is ENA measured to the 1 ...
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... BIN 25 8 BIN 26 9 BIN 27 10 BIN 28 11 GND 29 VCC 30 Plastic Quad Flatpack (Q2) S CREENING LF3304QC15 LF3304QC15G (GREEN) LF3304QC12 LF3304QC12G (GREEN) LF3304QC10 LF3304QC10G (GREEN) S CREENING LF3304QI10 12 LF3304 Dual Line Buffer/FIFO 80 VCC 79 GND 78 AOUT 0 77 AOUT 1 76 AOUT 2 75 AOUT 3 74 AOUT ...