lf3304 LOGIC Devices Incorporated, lf3304 Datasheet - Page 3

• Manufacturer Part Number: lf3304
• Description: Dual Line Buffer/fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
requires a Reset Read for initialization
because the read address pointer is
not defined at that time.
RWB — Reset Write B
See RWA Description.
RRB — Reset Read B
See RRA description.
OEA — Output Enable A
When OEA is LOW, AOUT
enabled for output. When OEA is
HIGH, AOUT
impedence state.
OEB — Output Enable B
When OEB is LOW, BOUT
enabled for output. When OEB is
HIGH, BOUT
impedence state.
Outputs
AOUT
AOUT
output port.
BOUT
BOUT
output port.
FIFO MODE
SIGNAL DEFINITIONS
Power
T
ADDRA
ABLE
0
1
x
x
11-0
11-0
11-0
11-0
2. L
— Data Output B
is the 12-bit registered data
— Data Output A
is the 12-bit registered data
ADDRB
11-0
11-0
OADING
x
x
0
1
is placed in a high-
is placed in a high-
P
LDA
ROGRAMMABLE
0
0
x
x
11-0
11-0
is
is
LDB
x
x
0
0
V
+3.3 V power supply. All pins must
be connected.
Clocks
WCLKA — Write Clock A
Data present on AIN
into the LF3304 on the rising edge of
WCLKA when the device is config-
ured for writing.
RCLKA — Read Clock A
Data is read from the LF3304 and pre-
sented on the output port (AOUT
after t
edge of RCLKA when the device is
configured for reading and the output
port is enabled. WCLKA and RCLKA
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
WCLKB — Write Clock B
Data present on BIN
into the LF3304 on the rising edge of
WCLKB when the device is config-
ured for writing.
RCLKB — Read Clock B
Data is read from the LF3304 and pre-
sented on the output port (BOUT
after t
edge of RCLKB when the device is
configured for reading and the output
port is enabled. WCLKB and RCLKB
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
F
WCLKA
CC
LAG
and GND
x
x
D
D
R
has elapsed from the rising
has elapsed from the rising
EGISTERS
WCLKB
x
x
3
11-0
11-0
Operation
PAEA Register
PAFA Register
PAEB Register
PAFB Register
is written
is written
11-0
11-0
)
)
Inputs
AIN
AIN
input port.
BIN
BIN
input port.
ADDRA — Address A
If LDA is LOW, on the rising edge
of WCLKA data present on AIN
written into the PAFA or PAEA regis-
ter depending on ADDRA (see Table
2). The LSB, AIN
the LSB of PAFA and PAEA registers.
The MSB, AIN
MSB of PAFA and PAEA registers.
ADDRB — Address B
If LDB is LOW, on the rising edge
of WCLKB data present on BIN
written into the PAFB or PAEB regis-
ter depending on ADDRB (see Table
2). The LSB, BIN
LSB of PAFB and PAEB registers. The
MSB, BIN
of PAFB and PAEB registers.
MODE
The mode select inputs determine the
operating mode of the LF3304 (Table
1) for data being input on the next clock
cycle. When switching between modes,
the internal pipeline latencies of the
device must be observed. After switch-
ing operating modes, either the user
must allow enough clock clycles to pass
to flush the internal RAM Array or RWx
and RRx must be driven LOW together
before valid data will appear on the out-
puts.
LENGTH — Non-Flag Pins
In FIFO Mode, the unused LENGTH
pins (LENGTH
LENGTH
Video Imaging Products
11-0
11-0
11-0
11-0
Dual Line Buffer/FIFO
1-0
— Data Input B
is the 12-bit registered data
— Data Input A
is the 12-bit registered data
5
11
— Mode Select
, LENGTH
, corresponds to the MSB
11
11
, corresponds to the
, LENGTH
0
0
, corresponds to the
, corresponds to
4
) must be tied
9/28/2005–LDS.3304-I
10
LF3304
,
11-0
11-0
is
is