lf3304 LOGIC Devices Incorporated, lf3304 Datasheet - Page 2

• Manufacturer Part Number: lf3304
• Description: Dual Line Buffer/fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LINE BUFFER MODE
SIGNAL DEFINITIONS
Power
V
+3.3 V power supply. All pins must
be connected.
Clocks
WCLKA — Write Clock A
WCLKA and RCLKA must be tied
together for RAM Array A to properly
operate as a Line Buffer. The rising
edge of xCLKA strobes all appropriate
enabled registers.
RCLKA — Read Clock A
See WCLKA description.
WCLKB — Write Clock B
WCLKB and RCLKB must be tied
together for RAM Array B to properly
operate as a Line Buffer. The rising
edge of xCLKB strobes all appropriate
enabled registers.
RCLKB — Read Clock B
See WCLKB description.
Inputs
AIN
AIN
input port.
BIN
BIN
input port.
LENGTH
The 12-bit value is used to specify the
length of each of the RAM Arrays. An
integer value ranging from 0 to 4095 is
used to select a delay ranging from 2
to 4097 clock cycles. The value placed
on LENGTH
delay minus 8. To set the length of
CC
11-0
11-0
11-0
11-0
and GND
— Data Input B
is the 12-bit registered data
— Data Input A
is the 12-bit registered data
11-0
11-0
— Line Buffer Length
is equal to the desired
RAM Array A the data presented on
LENGTH
on the active edge of WCLKA in con-
junction with LDA being driven LOW.
To set the length of RAM Array B
the data presented on LENGTH
loaded into the device on the active
edge of WCLKB in conjunction with
LDB being driven LOW. If an
equal length is desired for both
RAM Arrays, the data presented on
LENGTH
on the active edge of WCLK (WCLKA
and WCLKB tied together) in conjuc-
tion with LDx (LDA and LDB tied
together) being driven LOW.
MODE
The mode select inputs determine the
operating mode of the LF3304 (Table
1) for data being input on the next
clock cycle. When switching between
modes, the internal pipeline latencies
of the device must be observed. After
switching operating modes, either the
user must allow enough clock clycles
to pass to flush the internal RAM
Array or RWx and RRx must be
driven LOW together before valid
data will appear on the outputs.
Controls
LDA — RAM Array A Load
When LDA is LOW, data on
LENGTH
register on the rising edge of xCLKA.
LDB — RAM Array B Load
When LDB is LOW, data on
LENGTH
register on the rising edge of xCLKB.
WENA — Write Enable A
Driving WENA LOW places the
device in programmable delay mode
and driving WENA HIGH places
RAM Array A in recirculate mode
(programmable circular buffer).
When in recirculate mode, the write
1-0
11-0
11-0
11-0
11-0
— Mode Select
is loaded into the device
is loaded into the device
is latched in the length
is latched in the length
2
11-0
is
pointer position remains fixed while
data on AIN
switching back from recirculate mode
to delay mode, RWA and RRA should
be brought LOW to properly reset the
Write and Read pointers.
RENA — Read Enable B
In Line Buffer mode, RENA must be
kept LOW.
WENB — Write Enable B
Driving WENB LOW places the device
in programmable delay mode and
driving WENB HIGH places RAM
Array B in recirculate mode (pro-
grammable circular buffer). When in
recirculate mode, the write pointer
position remains fixed while data
on BIN
ing back from recirculate mode to
delay mode, RWB and RRB should be
brought LOW to properly reset the
Write and Read pointers.
RENB — Read Enable B
In Line Buffer mode, RENB must be
kept LOW.
RWA — Reset Write A
The write address pointer is reset to
the first physical location when RWA
is set LOW. After power up, the
LF3304 requires a Reset Write for ini-
tialization because the write address
pointer is not defined at that time.
RRA — Reset Read A
The read address pointer is reset to the
first physical location when RRA is set
LOW. After power up, the LF3304
T
ABLE
Video Imaging Products
MODE
0
0
1
1
Dual Line Buffer/FIFO
11-0
1. D
0
1
0
1
1-0
is ignored. When switch-
11-0
EVICE
Mode Select
Dual Line Buffer
Cascaded Line Buffer
Dual FIFO
Reserved
is ignored. When
C
ONFIGURATION
9/28/2005–LDS.3304-I
8
LF3304