xr16c872iq Exar Corporation, xr16c872iq Datasheet
xr16c872iq
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xr16c872iq Summary of contents
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... Embedded Systems ORDERING INFORMATION Part number Package Operating XR16C872CQ 100-Lead QFP 0° 70° C XR16C872IQ 100-Lead QFP -40° 85° Covered by U.S. patent number 5,649,122 and patent pending. 2 Windows is a trademark of Microsoft Corp. Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 ...
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XR16C872 ...
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D0-D7 A0-A15 IOR ISA Bus IOCHRDY IRQ3-7,9-12,15 ISA Bus DREQ0,1,3,5 Plug-and-Play DACK0,1,3,5# Controller EEPROM To External ...
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XR16C872 D0-D7 A0-A10 IOR IOCHRDY IRQ3 To ISA Bus IRQ4 IRQ5 IRQ7 ...
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PIN DESCRIPTION Signal Type Definition. The following signal type definitions are from the 872 device point of view. I Standard input O Standard active output OT24 Tri-state output IOP14 Tri-state bi-directional input/output IO24 Tri-state bi-directional input/output Name Pin # Type ...
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XR16C872 Name Pin Type IOCHRDY 20 OT24 RESET 1 I XTAL1 76 I XTAL2 75 O EED 73 Bidir EECLK 72 O EECS 71 Bidir MAN 1284 CONTROLLER INTERFACE PD7-PD0 32-34 IOP14 37-41 ACK# 51 ...
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Name Pin Type BUSY 50 IP24 ERR# 52 IP24 INIT# 45 IOP14 PE 49 IP24 SELECT 48 IP24 SELCTIN# 44 IOP14 STROBE# 47 IOP14 MODEM OR SERIAL PORT INTERFACE RXA, RXB 63,53 I TXA, TXB 64,54 O Rev. 1.00 DISCONTINUED ...
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XR16C872 Name Pin Type DTRA#, 65, O DTRB# 55 RTSA#, 66, O RTSB# 56 CTSA#, 67, I CTSB# 57 DSRA#, 68, I DSRB# 58 CDA#, 69, I CDB# 59 RIA#, 70, I RIB# 60 VCC 25,35,42 PWR 62,90 GND 16,26,36,43 ...
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FUNCTION DESCRIPTION The XR16C872 (872 highly integrated chip combining the functionality of two XR16C850 enhanced UART, an IEEE 1284 bi-directional printer interface, and the PC/ISA bus Plug-and-Play (PnP) interface. The PnP interface meets the Plug-and-Play ISA Specification Version ...
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XR16C872 Manual Configuration Mode Interface The 872 provides an input pin (MAN#) to bypass the auto configuration procedure. It changes address lines A12- A15 to manual configuration inputs S1-S4 and LPT. These inputs can be designed with external jumpers to ...
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A8-A15 ...
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XR16C872 UART The 872 UARTs are software compatible with the industry standard 16C550 on power up or reset. Each UART offers enhancements that are enabled through its Enhanced Features Registers. These features include transmit and receive FIFOs of 128 bytes, ...
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READ MODE Basic Registers (THR/RHR, FCR, IER/ISR, MCR/MSR, LCR/LSR, SPR/FCNT), accessible only when LCR bit-7 is set to logic Receive Holding Register Interrupt Enable Register Interrupt Status ...
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XR16C872 FIFO Operation The 128 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. The standard 16C550 provides only receive FIFO of 16 bytes with 4 selectable trigger levels and there is no transmit ...
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Two interrupts associated with RTS and CTS flow control have been added to give indication when RTS# pin or CTS# pin is de-asserted during operation. The RTS and CTS interrupts must be first enabled by EFR bit-4, and then enabled ...
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XR16C872 The UART compares each incoming receive character with Xoff-2 data match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal Register Table ...
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Output Output Baud Rate Baud Rate 16 x Clock MCR MCR BIT-7=1 Bit-7=0 50 200 75 300 150 600 300 1200 600 2400 1200 4800 2400 9600 4800 19.2K 7200 28.8K 9600 38.4k 19.2k 76.8k 38.4k 153.6k 57.6k 230.4k 115.2k ...
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XR16C872 The generator divides the input 16X clock by any divisor from -1. The UART divides the input clock by 16. 16 Further division of this 16X clock provides two table rates to support low and high ...
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DSR# inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 7). The CTS#, DSR#, CD#, and RI# are disconnected from their normal modem ...
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XR16C872 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the internal registers. UART A and B has same register set independently control. The assigned bit functions are defined in the following paragraphs. UART INTERNAL REGISTERS A2 ...
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UART INTERNAL REGISTERS (continue Register BIT-7 [Default] Note *3 Enhanced Registers are accessible only when LCR is set to 0xBF TRG [00] Trig FCTR [00] Rx/Tx Mode ...
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XR16C872 The UARTs have Device Identification and Device Revision code to distinguish the part with others suggested to the user to read the identification and revision information from the part only during the power on initialization routine to ...
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Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1; resetting IER bits 0- 3 enables the 850 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or ...
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XR16C872 Mode 1 Enable the interrupt in a block transfer mode operation. The transmit empty interrupt is set when the transmit FIFO trigger level is reached. The receive interrupt is set when the receive FIFO fills up to the programmed ...
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TRIGGER TABLE-D (Transmit) BIT-5 BIT-4 FIFO trigger level X X User programmable trigger levels FCR BIT 6-7: (logic 0 or cleared is the default condition, RX trigger level =8) These bits are used to set the trigger level for the ...
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XR16C872 Interrupt Status Register (ISR) The UART provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide ...
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LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. The upper unused bit(s) in the received data byte is set to zero. BIT-1 BIT-0 Word length ...
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XR16C872 Logic 1 = Force RTS# output to a logic 0. Automatic RTS may be used for hardware flow control by enabling EFR bit-6 (See EFR bit-6). MCR BIT-2: *OP1# output is not available in the 872. Logic 0 = ...
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LSR BIT-5: This bit is the Transmit Holding Register Empty indica- tor. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU ...
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XR16C872 MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the DSR# input pin. In the loop-back mode, this bit is the complement to the DTR bit in the MCR register. MSR BIT-6: RI (active ...
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EFR BIT-4: Enhanced function control bit. The content of the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 can be modified and latched. After modifying any bits in the enhanced registers, EFR bit-4 can be ...
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XR16C872 FCTR BIT-6: Scratch Pad Register (SPR) or EMSR select Scratch Pad Register (SPR) is selected as general read and write register. 16C550 compatible mode FIFO count register, Enhanced Mode Select Reg- ister (EMSR). Number of ...
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EMSR EMSR FCTR FCTR RTS Hysteresis Bit-5 Bit-4 Bit-1 Bit-0 (characters Next level +/- +/- +/- +/- ...
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XR16C872 1284 Controller The bi-directional parallel data port controller is compatible to IEEE Standard 1284 interface. The 1284 interface can be programmed as a standard printer port or bi-directional parallel port for high speed data transfer systems. The 1284 interface ...
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STANDARD DEFINITIONS Forward direction only. Compatible Mode, “Centronics” or standard mode (SPP). Reverse direction only. Nibble mode: 4 bits at a time using status lines for data “Hewlett Packard Bi-tronics”. Bi-directional. EPP: Enhanced Parallel Port, used primarily by non- printer ...
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XR16C872 This bit is forced to logic zero by ECR modes 000 or 010. It can be written only in ECR mode 001, and will maintain that state if the ECR mode is changed to 011, 100, or 110. This ...
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Cnfg-B Bit 3-5: In the PnP mode IRQ assignment is made through auto configuration. Manual mode defaults to IRQ 7. IOW# IOR# IRQ 000 001 7 001 001 7 (default) 010 010 7 011 001 7 100 001 7 101 ...
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XR16C872 OPERATION SPP MODE This is ECR mode 000 (system RESET mode). In this output-only mode the host data is registered to PD[7:0] at the trailing edge of IOW#; PDIR is driven low; STROBE#, AUTOFD#, INIT#, and SELCTIN# are open-drain; ...
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To prevent a system stall msecond TimeOut aborts the cycle if it expires before BUSY returns high. This TimeOut also sets bit 0 of DCR, which is cleared by disabling EPP mode or writing a high to DCR ...
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XR16C872 1284 CONTROLLER REGISTERS A10 REGISTER Data PD7 ECP-AFIFO DSR BUSY DCR EPP-APort AP EPP-DPort ...
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SPP” SIGNAL DESCRIPTIONS Signal Signal Description Name Type STROBE# O Active low. Indicates valid data is on the data lines. AUTOFD# O Active low. Instructs the printer to automatically insert a line feed for each carriage return. SELCTIN# O ...
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XR16C872 “NIBBLE MODE” SIGNAL DESCRIPTIONS Signal Signal Nibble mode name Type Name STROBE# O STROBE# AUTOFD# O HostBusy SELCTIN# O 1284Active INIT# O INIT# ACK# I PtrClk BUSY I PtrBusy PE I AckDataReq SELECT I Xflag ERR# I DataAvail# PD0-PD7 ...
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MODE” SIGNAL DESCRIPTIONS Signal Signal EPP mode name Type Name STROBE# O Write# AUTOFD# O DataStb# SELCTIN# O AddrStb# INIT# O Reset# ACK# I Intr# BUSY I Wait User defined SELECT I User defined ERR# I User ...
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XR16C872 “ECP MODE” SIGNAL DESCRIPTIONS Signal Signal ECP mode Name Type Name STROBE# O HostClk AUTOFD# O HostAck SELCTIN# O 1284Active INIT# O ReverseReq# ACK# I PeriphClk BUSY I PeriphAck PE I AckReverse# SELECT I Xflag ERR# I PeriphReq# PD0-PD7 ...
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UART Registers Reset Conditions REGISTER RESET STATE RHR 0xXX, X=random THR 0xXX, X=random IER 0x00 FCR 0x00 ISR 0x01 LCR 0x00 MCR 0x00 LSR 0x60 MSR 0xX0, X=state of input pins SPR 0xFF DLL 0xXX, X=random DLM 0xXX, X=random TRG ...
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XR16C872 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation (100-PQFP) * thermal resistance: theta-ja theta-jc DC ELECTRICAL CHARACTERISTICS T =0° - 70° C (-40° - +85°C for IQ package), Vcc=3.3 or 5.0 V ...
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HOST INTERFACE AND UART AC Electrical Characteristics T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T Clock pulse duration 1CW T Oscillator/Clock frequency 2FQ T ...
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XR16C872 1284 Controller AC Electrical Characteristics T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T20 PD7-PD0, STROBE#, AUTOFD#, INIT, SLCTIN# delay from IOW# inactive T21 ...
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Controller AC Electrical Characteristics (continue) Symbol Parameter T51 IOW# inactive to Host command active (IOW# or IOR#) T52 IOCHRDY pre-charge width at release T53 Host address setup to IOR# active T54 Host address hold from IOR# active T55 Host ...
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XR16C872 T1CW EXTERNAL CLOCK Rev. 1.00 DISCONTINUED Valid ...
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A0-A15 T3AS D0-D7 Active Change of state Outputs Inputs I ...
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XR16C872 R X INT Receive Data Timing in DMA Mode 0 RX Data fills Characters Delay INT Receive Data Timing in FIFO and DMA Mode 1 ...
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Interrupt ...
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XR16C872 Start Bit Time 1/2 Bit Time Bit Time 0-1 16x clock delay Start Rev. 1.00 DISCONTINUED ...
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PD0 IRQx Parallel port timing in SPP, PS/2 mode ...
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XR16C872 PD0-PD7 T 27 STROBE# BUSY Parallel port forward timing in ECP mode Rev. 1.00 DISCONTINUED T ...
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Parallel port reverse timing in ECP mode A0-2, A10 ...
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XR16C872 A0-2, A10 Address or data read timing in EPP mode Rev. 1.00 DISCONTINUED ...
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Rev. 1.00 DISCONTINUED Visit Exar Web Site at www.exar.com 59 XR16C872 ...
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... XR16C872 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...