xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 24

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

XR16C872
mode operation. The transmit empty interrupt is set
when the transmit FIFO trigger level is reached. The
receive interrupt is set when the receive FIFO fills up to
the programmed trigger level. However the FIFO contin-
ues to fill regardless of the programmed level until the
FIFO is completely full.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This bit
must be a “1” when other FCR bits are written to or they
will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the FIFO counter and resets the
pointers logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the
FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the FIFO counter and resets the
pointers logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing
the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condition)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
This selects single character interrupt operation. The
transmit empty interrupt will be set when the UART is
set in this 16C450 or single character simulation mode
(FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO
mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and when there are no characters in the transmit
FIFO or transmit holding register.
Receive operation in mode “0”:
When the UART is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic
0) and there is a character in RHR, the receive ready
interrupt is generated.
Mode 1
Rev. 1.00
Enable the interrupt in a block transfer
DISCONTINUED
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Transmit operation in mode “1”:
When the UART is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the transmit empty interrupt is
generated when the transmit FIFO reaches its trigger
level.
Receive operation in mode “1”:
When the UART is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the receive trigger level has been
reached, or a Receive Time Out has occurred, the
receive ready interrupt is generated.
FCR BIT 4-5: (logic 0 or cleared is the default condition,
TX trigger level = none)
The XR16C850 provide 4 user selectable trigger levels,
The FCTR Bits 4-5 selects one of the following table.
These bits are used to set the trigger level for the transmit
FIFO interrupt. The UART will issue a transmit empty
interrupt when number of characters in FIFO drops
below the selected trigger level.
TRIGGER TABLE-A (Transmit)
“Default setting after reset, ST16C550 mode”
TRIGGER TABLE-B (Transmit)
TRIGGER TABLE-C (Transmit)
BIT-5
BIT-5
BIT-5
X
0
0
1
1
0
0
1
1
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BIT-4
BIT-4
BIT-4
X
0
1
0
1
0
1
0
1
FIFO trigger level
FIFO trigger level
FIFO trigger level
None
16
24
30
16
32
56
8
8