xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 14

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

XR16C872
FIFO Operation
The 128 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. The standard
16C550 provides only receive FIFO of 16 bytes with 4 selectable trigger levels and there is no transmit trigger level
selection. The 872 UART provides independent programmable trigger levels from 0 to 128 for both receiver and
transmitter. When receive or transmit data has reached the preset trigger level the UART generates an interrupt
to call for service. The receive FIFO section includes a time-out function to ensure data is delivered to the CPU.
A receive data time-out interrupt is generated when there is no receive data for a period of about 4-characters but
the Receive Holding Register (RHR) is full or data did not reached the receive trigger level. See in the timing diagram
area for TX and RX FIFO operation.
Hardware (RTS/CTS) Flow Control Operation
Automatic hardware or RTS and CTS flow control is used to prevent data overrun to the local receiver FIFO and
remote receiver FIFO. The RTS# output pin is used to request remote unit to suspend/restart data transmission
while the CTS# input pin is monitored to suspend/restart local transmitter. The auto RTS and auto CTS flow control
features are individually selected to fit specific application requirement and enabled through EFR bit-6 and 7. The
auto RTS function must be started by asserting RTS# pin (MCR bit-1=1) after it is enabled.
Rev. 1.00
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to
CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and
fills UART-A receive FIFO (4). When RXA data fills to up its receive FIFO trigger level, UARTA activates its
RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is
long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of
RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data
transfer. UART-B stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO
data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-assert RTSA# (10)
CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next RX trigger (12).
This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA#
controlling the data flow.
( R X A F I F O
R T S A #
C T S B #
R X A F I F O
I n t e r r u p t )
T X B
I N T A
T r i g g e r R e a c h e d
R e c e i v e r F I F O
T r i g g e r L e v e l
L o c a l U A R T
T r a n s m i t t e r
A u t o C T S
A u t o R T S
U A R T A
M o n i t o r
R e c e i v e D a t a
A s s e r t R T S # t o B e g i n T r a n s m i s s i o n
S t a r t s
1
2
3
T r i g g e r L e v e l
4
R X F I F O
R T S A #
T X A
C T S A #
O N
R X A
O N
DISCONTINUED
5
R T S H i g h
T h r e s h o l d
7
14
6
8
O F F
S u s p e n d
O F F
R T S B #
C T S B #
T h r e s h o l d
R T S L o w
R X B
T X B
R e s t a r t
9
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1 0
1 1
R e m o t e U A R T
T r i g g e r R e a c h e d
T r i g g e r L e v e l
O N
R e c e i v e r F I F O
T r a n s m i t t e r
A u t o C T S
A u t o R T S
U A R T B
1 2
M o n i t o r
O N
T r i g g e r L e v e l
R X F I F O