xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 37

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

Cnfg-B Bit 3-5:
In the PnP mode IRQ assignment is made through auto
configuration. Manual mode defaults to IRQ 7.
Cnfg-B Bit-6:
Returns the true value of the selected IRQ pad.
Cnfg-B Bit-7:
Indicates RLE compression is not supported.
EXTENDED CONTROL REGISTER ( ECR )
The Extended Control Register has a system RESET
state of 10010101. The significance of the bits is defined
by the ECP specification as:
ECR Bit-0:
This read-only bit returns FIFO empty status (FIFO-E)
and is forced high unless PPF, ECP, or TST mode is
selected.
0 = At least one byte of data contains in the FIFO.
1 = FIFO is empty.
ECR Bit-1:
This read-only bit returns FIFO full status (FIFO-F) and
is forced low unless PPF, ECP, or TST mode is
selected.
0 = At least one empty location is available in the FIFO.
1 = FIFO is full.
ECR Bit-2:
When low, this bit (ServiceIntr) enables a pulsed inter-
rupt and enables DMA requests (if bit-3 is set). If the
enabled interrupt occurs, this bit is automatically re-
turned to a high. The interrupt conditions are:
Rev. 1.00
IOW#
000
001
010
011
100
101
110
111
IOR#
001
001
010
001
001
001
001
111
IRQ
7
7 (default)
7
7
7
7
7
7
DISCONTINUED
37
ECR Bit-3 = DMA
DCR Bit-5 = DIRection
ECR BIT-3:
This bit disables DMA when set low. When set high, a
low on ServiceIntr will enable DMA requests.
0 = DMA disabled, DRQx pin is three-stated.
1 = DMA enabled
ECR Bit-4:
When low, this bit (ErrIntrEn#) enables a pulsed inter-
rupt if ERR# (Fault#) is low. The interrupt is only enabled
in ECP mode.
ECR Bit 5-7:
This field can be set to any value if the current value is
000 or 001. If the current value is not 000 or 001, then
the field can only be written to 000 or 001. The modes
are defined as:
DMA
MODE
000
001
010
011
100
101
110
111
0
0
1
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DIR
NAME
SPP
PS2
PPF
ECP
EPP
-
TST
CFG
X
0
1
CONDITION
8 empty bytes in the FIFO.
8 filled bytes in the FIFO.
DMA Terminal Count (TC).
DESCRIPTION
Standard, output only. DCR
Bit-5 is forced to “0”.
Bi-directional PS/2 parallel
port. FIFO is disabled
FIFOed, output only. DCR Bit-
5 is forced to “0”.
ECP FIFOed port with RLE de-
compression. FIFO direction
is controlled by DCR Bit-5.
EPP mode.
reserved
FIFO test mode. FIFO is ac-
cessible via TFIFO register.
Configuration A/B register en-
able.
XR16C872