sc16c2552b NXP Semiconductors, sc16c2552b Datasheet
sc16c2552b
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sc16c2552b Summary of contents
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... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2552B operates 3.3 V and 2.5 V, and the Industrial temperature range, and is available in a plastic PLCC44 package. 2. Features Industrial temperature range ( + ...
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... REGISTER CS SELECT CHSEL LOGIC INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 1. SC16C2552B block diagram. 9397 750 14442 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs TRANSMIT FIFO REGISTERS RECEIVE FIFO REGISTERS CLOCK AND BAUD RATE ...
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... I Chip Select (Active-LOW). This function is selects channel ‘A’ or ‘B’, in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the SC16C2552B. D0-D7 2-9 I/O Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for transferring information to or from the controlling CPU ...
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... IOR 24 I Read strobe (Active-LOW). A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0-A2 onto the SC16C2552B data bus (D0-D7) for access by external CPU. IOW 20 I Write strobe (Active-LOW). A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defi ...
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... O Data Terminal Ready (Active-LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the SC16C2552B is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset ...
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... The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C2552B is capable of operation to 1.5 Mbit/s with a 24 MHz crystal. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460 ...
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... Philips Semiconductors 6.2 Internal registers The SC16C2552B provides two sets of internal registers (A and B) consisting of 13 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status ...
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... TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock MHz, as required for supporting a 5 Mbit/s data rate. The SC16C2552B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external ...
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... Rev. 02 — 13 December 2004 SC16C2552B 002aaa125 DLM DLL program value program value (HEX) (HEX ...
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... Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2552B sets the interrupt output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level ...
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... REGISTERS REGISTER RECEIVE RECEIVE FIFO REGISTERS REGISTER CONTROL CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 02 — 13 December 2004 SC16C2552B TXA, TXB SHIFT MCR[ SHIFT RXA, RXB RTSA, RTSB CTSA, CTSB DTRA, DTRB MODEM DSRA, DSRB LOGIC OP1A, OP1B RIA, RIB ...
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... Set A is accessible when CHSEL is a logic 1, and Set B is accessible when CHSEL is a logic 0. 9397 750 14442 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs details the assigned bit functions for the SC16C2552B internal registers. The Bit 7 Bit 6 Bit 5 ...
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... The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2552B and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... ISR register loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2552B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
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... Logic 0 = Set DMA mode ‘0’ (normal default condition). Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C2552B is in the 16C450 mode (FIFOs disabled; FCR[0] = logic the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0 ...
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... FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C2552B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 02 — 13 December 2004 SC16C2552B Table 13). Table 14). Table 15). © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output TX and the receiver input RX, CTS, DSR, CD, and RI are disconnected from the SC16C2552B I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2552B and the CPU. Table 17: Bit 9397 750 14442 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Line Status Register bits description ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C2552B has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR Logic DSR change (normal default condition). ...
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... Philips Semiconductors 7.9 Scratchpad Register (SPR) The SC16C2552B provides a temporary data register to store 8 bits of user information. 7.10 Alternate Function Register (AFR) This is a read/write register used to select specific modes of MF operation and to allow both UART register’s sets to be written concurrently. Table 19: ...
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... Philips Semiconductors 7.11 SC16C2552B external reset conditions Table 21: Register IER ISR LCR MCR LSR MSR FCR AFR Table 22: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB TXRDYA, TXRDYB 8. Limiting values Table 23: In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... 0.4 OL (databus 1 0.4 OL (other outputs (databus (other outputs 800 A 1. (data bus 400 A 1. (other outputs MHz - 3 Rev. 02 — 13 December 2004 SC16C2552B 3.3 V 5.0 V Unit Min Max Min Max 0.3 0.6 0.5 0.6 V 2 0.3 0.8 0.5 0.8 V 2 ...
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... Rev. 02 — 13 December 2004 SC16C2552B 3.3 V 5.0 V Unit Min Max Min Max MHz ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs t 6h VALID ADDRESS t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA t 6h VALID ADDRESS t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 02 — 13 December 2004 SC16C2552B 002aaa128 002aaa127 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs t 17d change of state change of state t 18d active t active Rev. 02 — 13 December 2004 SC16C2552B change of state t 18d active active 19d active active t 18d change of state 002aaa352 002aaa112 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... data bits 6 data bits 7 data bits 16 baud rate clock DATA BITS (5– Rev. 02 — 13 December 2004 SC16C2552B next data parity stop start bit bit bit D7 t 20d active t 21d active 002aaa113 NEXT DATA START ...
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... data bits 6 data bits 7 data bits active transmitter ready t 22d t 23d 16 baud rate clock Rev. 02 — 13 December 2004 SC16C2552B PARITY STOP BIT BIT D6 D7 FIRST BYTE THAT REACHES THE TRIGGER LEVEL t 25d ACTIVE DATA READY t 26d ACTIVE 002aaa579 ...
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... Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs DATA BITS (5- 27d ACTIVE TRANSMITTER READY Rev. 02 — 13 December 2004 SC16C2552B NEXT DATA PARITY STOP START BIT BIT BIT 28d TRANSMITTER NOT READY 002aaa580 © ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 02 — 13 December 2004 SC16C2552B PARITY STOP BIT BIT D6 D7 002aaa581 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.656 0.656 0.63 0.63 0.695 0.695 0.048 0.05 0.650 0.650 0.59 0.59 0.685 0.685 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 02 — 13 December 2004 SC16C2552B SOT187 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1. ...
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... Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 2.5 mm Rev. 02 — 13 December 2004 SC16C2552B 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, USON, VFBGA , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 02 — 13 December 2004 SC16C2552B Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5][6] not recommended suitable ...
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... Product data (9397 750 11966) 9397 750 14442 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 10 C measured in the atmosphere of the reflow Rev. 02 — 13 December 2004 SC16C2552B © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Rev. 02 — 13 December 2004 SC16C2552B Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Scratchpad Register (SPR 7.10 Alternate Function Register (AFR 7.11 SC16C2552B external reset conditions . . . . . 23 © Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...