sc16c2552b NXP Semiconductors, sc16c2552b Datasheet - Page 8

• Manufacturer Part Number: sc16c2552b
• Description: Sc16c2552b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14442
Product data
6.3 FIFO operation
6.4 Time-out interrupts
6.5 Programmable baud rate generator
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. A time-out interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character, or a receive trigger interrupt is generated when Rx FIFO level
is equal to the program Rx trigger value.
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset if the transmitter interrupt is enabled, the SC16C2552B
will issue an interrupt to indicate that Transmit Holding Register is empty. The ISR
register provides the current singular highest priority interrupt only. It could be noted
that a condition can exist where a higher priority interrupt may mask the lower priority
interrupt(s). Only after servicing the higher pending interrupt will the lower priority
interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C2552B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
The SC16C2552B supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
A baud rate generator is provided for each UART channel, allowing independent
TX/RX channel control. The programmable Baud Rate Generator is capable of
accepting an input clock up to 80 MHz, as required for supporting a 5 Mbit/s data
rate. The SC16C2552B can be configured for internal or external clock operation. For
internal clock oscillator operation, an industry standard microprocessor crystal is
connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for
standard or custom rates (see
The generator divides the input 16 clock by any divisor from 1 to 2
SC16C2552B divides the basic external clock by 16. The basic 16 clock provides
table rates to support standard and custom applications using the same system
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 02 — 13 December 2004
Table
5).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C2552B
16
1. The
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