ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 10

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Interrupts
This device provides external interrupts (INT pin inter-
rupt, A/D Converter interrupt, Serial Interface interrupt)
and internal timer/event counter interrupts. The Interrupt
Control Register0 (INTC0;0BH) and interrupt control
register1 (INTC1:1EH) both contain the interrupt control
bits that are used to set the enable/disable status and in-
terrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 or INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the stack pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
Rev. 1.30
Bit No.
Bit No.
3, 7
0
1
2
3
4
5
6
7
0
1
2
4
5
6
Label
Label
USBF
ES2II
ET0I
ET1I
SI2F
ESII
EMI
T0F
T1F
EEI
EIF
EUI
SIF
Controls the master (global) interrupt (1= enable; 0= disable)
Controls the external interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable)
External interrupt request flag (1= active; 0= inactive)
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
Unused bit, read as 0
Control the USB interrupt (1= enable; 0= disable)
Control Serial interface interrupt (1= enabled; 0= disabled)
Control Serial interface 2 interrupt (1= enabled; 0= disabled)
Unused bit, read as 0
USB interrupt request flag (1= active; 0= inactive)
Serial interface interrupt request flag (1= active; 0= inactive)
Serial interface 2 interrupt request flag (1= active; 0= inactive)
INTC0 (0BH) Register
INTC1 (1EH) Register
10
External interrupts can are triggered by a falling edge
transition of INT), and the related interrupt request flag
(EIF; bit4 of the INTC0) is set as well. After the interrupt
is enabled, the stack is not full, and the external interrupt
is active (INT pin), a subroutine call at location 04H oc-
curs. The interrupt flag (EIF) and EMI bits are all cleared
to disable other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initialized
by setting the Timer/Event Counter 0 interrupt request
flag (bit 5 of the INTC0), caused by a Timer 0 overflow.
When the interrupt is enabled, the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The internal Timer/Event Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of the INTC0), caused by a Timer 1 overflow.
When the interrupt is enabled, the stack is not full and the
T1F is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC1) will be set.
The access of the corresponding USB FIFO from PC
The USB suspend signal from the PC
The USB resume signal from the PC
USB Reset signal
Function
Function
HT82A523R
May 13, 2008