ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 26

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Options
The following table shows all kinds of options in the microcontroller. All of the OTP options must be defined to ensure a
proper functioning system. The default values of the options are 0 .
Note:
Rev. 1.30
No.
26*
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
1
2
3
4
5
6
7
8
9
*: The purpose of this option is to enable the endpoint that will be used, and disable the endpoint that will not be
PA0~PA7 pull-high resistor enable or disable (by bit) (default non-pull-high)
PB0~PB7 pull down resistor enable or disable (by bit) (default non-pull-high)
PC0~PC7 pull-high resistor enable or disable (by nibble) (default non-pull-high)
PD0~PD7 pull-high resistor enable or disable (by nibble) (default non-pull-high)
PE0~PE7 pull-high resistor enable or disable (by nibble) (default non-pull-high)
LVR enable or disable (default disable)
CLK enable or disable (if CLK enable then PB0 I/O port will be disable) (default disable)
SIO (Serial Interface) enable or disable (if SIO is enabled then PE0~PE3 I/O port will be disabled)
(default disable)
SIO2 (Serial Interface 2) enable or disable (if SIO2 enable then PC4~PC7 I/O port will be disable)
(default disable), 0=disable; 1=enable
SIO_ CPOL: Clock polarity 1/0: clock polarity rising or falling edge (default falling edge)
SIO_ CPOL2: Clock polarity 1/0 : clock polarity rising/falling edge (default falling edge 0 )
0=falling edge 1=rising edge
SIO_WCOL: enable or disable (default disable)
SIO_WCOL2: enable or disable (default disable 0 )
0=disable; 1=enable
SIO_CSEN: enable or disable, CSEN mask option is used to enable/disable (1/0) software CSEN function
(default disable)
SIO_CSEN2: enable or disable, CSEN mask option is used to enable/disable software CSEN function (de-
fault disable 0 )
0=disable; 1=enable
WDT enable or disable (default disable)
WDT clock source: f
WDT timeout period: 2
PA0~PA7 wake-up enable or disable (by bit) (default disable)
PB0~PB7 wake-up enabled or disabled (by nibble) (default disable)
0= non-wakeup; 1=wake-up
PB0~PB7 output structures: CMOS/NMOS (by bit) (default NMOS 0 )
0=NMOS; 1=CMOS
PC0~PC7 wake-up enabled/disabled (by nibble) (default disable 0 )
0=non-wakeup; 1=wakeup
PD0~PD7 wake-up enabled/disabled (by nibble) (default disable 0 )
0=non-wakeup; 1=wakeup
PE0~PE7 wake-up enabled/disabled (by nibble) (default disable 0 )
0=non-wakeup; 1=wakeup
EP1~EP3 Data pipe enable: EP1, EP2, EP3 enable or disable. (default is enable)
PSYNC Enable/Disable (if PSYNC Enable then PA0 I/O port will be disable and the rising edge of PSYNC is
used to synchronize the SBDR data) (default disable)
Table High Byte Pointer for Current Table Read (TBHP)
0=disable; 1=enable
used (USB chapter 8 will test this function).
CLRWDT instruction (s): 1 or 2 (default 1 instruction)
SYS
12
/4 or WDTOSC (default WDTOSC)
~2
13
/f
S
(00), 2
13
~2
14
/f
S
26
(01), 2
Option
14
~2
15
/f
S
(10), 2
15
~2
16
/f
S
(11) (default 2
HT82A523R
May 13, 2008
12
~2
13
/f
S
)