ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 12

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a warm reset
and only the Program Counter and Stack Pointer are re-
set to zero. To clear the contents of WDT, three methods
are adopted; external reset (a low level to RES), soft-
ware instructions, or a HALT instruction. The software
instructions include CLR WDT and the other set CLR
WDT1 and CLR WDT2 . Of these two types of instruc-
tion, only one can be active depending on the option
selected (i.e. CLRWDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In case
must be executed to clear the WDT, otherwise, the WDT
may reset the chip due to time-out.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system can quit the HALT mode in many ways, by an
external reset, an interrupt (except serial interface inter-
rupt and serial interface 2 interrupt), an external falling
edge or rising edge signal on I/O ports or a WDT over-
flow. An external reset causes a device initialization and
the WDT overflow performs a warm reset . After exam-
ining the TO and PDF flags, the cause for a chip reset can
be determined. The PDF flag is cleared by a system
power-up or by executing the CLR WDT instruction and
is set when executing the HALT instruction. On the
other hand, the TO flag is set if the WDT time-out occurs,
Rev. 1.30
CLR WDT times selection option . If the CLR WDT is
CLR WDT1 and CLR WDT2 are chosen (i.e.
CLRWDT times equal two), these two instructions
The system oscillator is turned off but the WDT oscil-
lator keeps running (if the WDT oscillator or the real
time clock is selected).
The contents of the on-chip RAM and registers remain
unchanged.
The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the
real time clock).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
Watchdog Timer
12
and causes a wake-up that only resets the Program
Counter and Stack Pointer; and leaves the others in their
original status.
The Port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in Port A can be independently selected to wake-up the
device by option. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequences may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. But if the interrupt is
enabled and the stack is not full, a regular interrupt re-
sponse takes place. When an interrupt request flag is
set to 1 before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. If a
wake-up event occurs, it takes 1024 f
period) to resume normal operation. In other words, a
dummy period is inserted after wake-up. If the wake-up
results from an interrupt acknowledge, the actual inter-
rupt subroutine execution is delayed by more than one
cycle. However, if the wake-up results in the next in-
struction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur:
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a warm reset that
resets only the program counter and stack pointer, leav-
ing the other circuits in their original state. Some regis-
ters remain unaffected during any other reset
conditions. Most registers are reset to the initial condi-
tion when the reset conditions are met. Examining the
PDF and TO flags, the program can distinguish between
different chip resets .
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
HT82A523R
SYS
(system clock
May 13, 2008