ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 19

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Clock polarity= rising (CLK) or falling (CLK): 1 or 0 (mask option)
WCOL: master/slave mode, set while writing to SBDR
when data is transferring (transmitting or receiving) and
this writing will then be ignored. WCOL function can be
enabled/disabled by mask option. WCOL is set by SIO
and cleared by users.
Data transmission and reception are still working when
the MCU enters the HALT mode.
CPOL is used to select the clock polarity of CLK. It is a
mask option.
MLS: MSB or LSB first selection
CSEN: chip select function enable/disable, CSEN=1
SCSA signal function is active. Master should output
SCSA signal before CLK signal is set and slave data
transferring should be disabled (or enabled) before (af-
ter) SCSA signal is received. CSEN= 0, SCSA signal is
not needed, SCSA pin (master and slave) should be
floating. CSEN has 2 options: CSEN mask option is
used to enable/disable software CSEN function. If
CSEN mask option is disabled, the software CSEN is al-
ways disabled. If CSEN mask option is enabled, soft-
ware CSEN function can be used.
Rev. 1.30
Modes
Master
Slave
4.
2.
3.
4.
5.
6.
7.
8.
1.
2.
3.
5.
6.
7.
8.
9.
1.
9.
Select CKS and select M1, M0 = 00,01,10
Select CSEN, MLS (the same as the slave)
Set SBEN
Writing data to SBDR
step 5
buffer
Check WCOL; WCOL= 1
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
CKS don t care and select M1, M0= 11
Select CSEN, MLS (the same as the master)
Set SBEN
Writing data to SBDR
SCSA): CLK
TXRX buffer and SDIA data is shifted into TXRX buffer
latched into SBDR)
Check WCOL; WCOL= 1
Check TRF or wait for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
(SIO internal operation
data transferred, data in TXRX buffer is latched into SBDR)
go to step 5
Operation of Serial Interface
data is stored in TXRX buffer
data is stored in TXRX buffer
clear WCOL and go to step 4; WCOL= 0
clear WCOL, go to step 4; WCOL= 0
(SIO internal operations
data stored in TXRX buffer, and SDIA data is shifted into TXRX
19
Operations
SBEN= 1
SCSA= floating (CSEN= 0); SDIA= floating; SDOA= 1;
master CLK= output 1/0 (dependent on CPOL mask op-
tion), slave CLK= floating
SBEN= 0
CLK= floating
TRF is set by SIO and cleared by users. When data
transfer (transmission and reception) is completed, TRF
is set to generate SBI (serial bus interrupt).
If the PSYNC option is enabled, use the SYNC signal to
synchronize the SDBR (the next data which the SDBR
receives will be bit7). Please refer to the following timing
(only for the SPI interface which is pin-shared with port
E.):
The SYNC signal is used to synchronize the SDBR
when both the HT82A523R is working under slave
mode and PSYNC option is enabled. Otherwise, if the
HT82A523R is working under master mode, the PSYNC
option is ignored and the SYNC signal is not used to
synchronize the SDBR.
serial bus disabled; SCSA= SDIA= SDOA=
serial bus standby; SCSA (CSEN= 1) = 1;
output CLK (and SCSA) signals
data transferred, data in TXRX buffer is
CLK (SCSA) received
waiting for master clock signal (and
go to step 6
go to step 6
HT82A523R
output data in
May 13, 2008
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