ht82j31a Holtek Semiconductor Inc., ht82j31a Datasheet
ht82j31a
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ht82j31a Summary of contents
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... The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, SPI interface, Selection Table System Program Part No. VDD Clock Memory 4MHz~ HT82J31A 2.2v~5. 12MHz Rev. 1.00 16 Channel A/D MCU with SPI Interface Up to 0.5 s instruction cycle with 8MHz system clock 6-level subroutine nesting ...
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... Block Diagram Pin Assignment Rev. 1.00 2 September 19, 2007 HT82J31A ...
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... OSC2 can be used to measure the system clock at 1/4 frequency. Negative power supply, ground Schmitt trigger reset input. Active low Positive power supply +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 3 HT82J31A September 19, 2007 ...
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... V =0. =0. Test Conditions Min. V Conditions DD 2.2V~2.7V 400 2.8V~5.5V 400 2.7V~5.5V 1000 2.2V~2.7V 0 2.8V~5. Wake-up from HALT 1 4 HT82J31A Ta=25 C Typ. Max. Unit 5 ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. System Clocking and Pipelining Instruction Fetching 5 HT82J31A September 19, 2007 ...
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... Program Counter + 2 PC8 @ Program Counter 6 HT82J31A ...
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... The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read The following diagram illustrates the addressing/data flow of the look-up table: 7 September 19, 2007 HT82J31A ...
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... The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] in- struction is executed. Table Location Bits PC8 @ Table Location 8 HT82J31A September 19, 2007 ...
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... Data Memory is fully accessible by the user pro- gram for both read and write operations. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory 9 September 19, 2007 HT82J31A ...
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... However, it must be noted that when the Memory Pointer for these devices is read, bit 7 will be read as high. ; setup size of block ; setup memory pointer with first RAM address ; clear the data at address defined increment memory pointer ; check if last memory location has been cleared 10 HT82J31A September 19, 2007 ...
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... OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by a system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Status Register 11 HT82J31A September 19, 2007 ...
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... PCC, PDC and PFC, to control the input/output configu- ration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is directly mapped to a bit in its associ- ated port control register. 12 September 19, 2007 HT82J31A ...
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... PFD configuration option has been selected. I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. 13 HT82J31A September 19, 2007 ...
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... The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 00H to FFH the preload register must first be cleared to 00H. It should be noted that after power-on the preload register 14 September 19, 2007 HT82J31A ...
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... When the timer is full and over- flows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be Timer Mode Timing Chart 15 HT82J31A September 19, 2007 ...
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... In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logi- cal transitions on the PA4/TMR pin and not by the logic level. Event Counter Mode Timing Chart 16 HT82J31A September 19, 2007 ...
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... The same applies if the timer is configured the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. PFD Output Control 17 HT82J31A September 19, 2007 ...
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... Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter the timer mode, which uses the internal system clock as the clock source. 18 September 19, 2007 HT82J31A ...
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... Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. Function INTC0 Register 19 HT82J31A Priority Vector 1 004H 2 008H 3 ...
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... SPI_A interrupt vector at location 10H, will take place. For an SPI_B interrupt, a subroutine call to the SPI_B interrupt vector at location 14H, will take place. When the interrupt is serviced, the SPI interrupt request flag, SIF_A or SIF_B, will be automatically reset 20 HT82J31A September 19, 2007 ...
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... Note that as the external reset pin is also pin-shared with PA7 used as a reset pin, the correct reset configuration option must be selected. If the configuration option selects this pin I/O pin, Reset Circuit 21 September 19, 2007 HT82J31A ...
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... To ensure reliable continuation of normal program execution after a reset occurs important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. 22 September 19, 2007 HT82J31A ...
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... HT82J31A RES Reset WDT Time-out (HALT) (HALT)* 000H 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...
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... There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruc- tion in the application program. When this instruction is executed, the following will occur: The system oscillator will stop running and the appli- cation program will stop at the HALT instruction. 24 HT82J31A September 19, 2007 ...
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... If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. 25 September 19, 2007 HT82J31A ...
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... CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR Watchdog Timer 26 HT82J31A September 19, 2007 ...
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... To Disable the SPI bus SCK, SDI, SDO, SCS floating. SPI Operation All communication is carried out using the 4-line inter- face for both Master or Slave Mode. The timing diagram shows the basic operation of the bus. SPI Block Diagram 27 HT82J31A September 19, 2007 ...
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... Baud rate. Values of 00 can be selected. Step 3. Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be same as the Slave device. Step 4. Setup the SBEN bit in the SBCR control register to enable the SPI interface. 28 HT82J31A September 19, 2007 ...
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... SPI_A WCOL bit: enable or disable 15 SPI_A CSEN bit: enable or disable SPI_A SCK clock polarity: rising edge or falling 16 edge 17 SPI_B: enable or disable 18 SPI_B WCOL bit: enable or disable 19 SPI_B CSEN bit: enable or disable SPI_B SCK clock polarity: rising edge or falling 20 edge 29 September 19, 2007 HT82J31A ...
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... Application Circuits Rev. 1.00 30 September 19, 2007 HT82J31A ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 31 September 19, 2007 HT82J31A ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 32 HT82J31A Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 33 HT82J31A Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 34 September 19, 2007 HT82J31A ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 35 HT82J31A September 19, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82J31A September 19, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 37 HT82J31A September 19, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 38 HT82J31A September 19, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 39 HT82J31A September 19, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT82J31A September 19, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT82J31A September 19, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 42 HT82J31A September 19, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 43 September 19, 2007 HT82J31A ...
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... Package Information 28-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 697 HT82J31A Max. 419 300 20 713 104 September 19, 2007 ...
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... SKDIP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 1375 278 125 125 16 50 100 295 330 0 45 HT82J31A Max. 1395 298 135 145 20 70 315 375 15 September 19, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 46 September 19, 2007 HT82J31A ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 47 September 19, 2007 HT82J31A ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 48 September 19, 2007 HT82J31A ...