ht82j31a Holtek Semiconductor Inc., ht82j31a Datasheet - Page 16

• Manufacturer Part Number: ht82j31a
• Description: 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

generated. The timer interrupt can be disabled by ensur-
ing that the ETI bit in the INTC register is cleared to zero.
It should be noted that a timer overflow is one of the
wake-up sources.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on external pin PA4/TMR, can be re-
corded by the internal timer. For the timer to operate in
the event counting mode, bits TM1 and TM0 of the
TMRC register must be set to 0 and 1 respectively. The
timer-on bit, TON must be set high to enable the timer to
count. With TE low, the counter will increment each time
the PA4/TMR pin receives a low to high transition. If the
TE bit is high, the counter will increment each time
PA4/TMR receives a high to low transition. As in the
case of the other two modes, when the counter is full
and overflows, the timer will be reset to the value al-
ready loaded into the preload register and continue
counting. If the timer interrupt is enabled, an interrupt
signal will also be generated. The timer interrupt can be
disabled by ensuring that the ETI bit in the INTC register
is cleared to zero. To ensure that the external pin
PA4/TMR is configured to operate as an event counter
input pin, two things have to happen. The first is to en-
sure that the TM0 and TM1 bits place the timer/event
counter in the event counting mode, the second is to en-
sure that the port control register configures the pin as
an input. It should be noted that a timer overflow is one
of the wake-up sources. In the Event Counting mode,
the Timer/Event Counter will continue to record exter-
nally changing logic events on the timer input pin, even if
the microcontroller is in the Power Down Mode. As a re-
sult when the timer overflows it will generate a wake-up
and if the interrupts are enabled also generate a timer
interrupt signal.
Rev. 1.00
Pulse Width Measure Mode Timing Chart
Event Counter Mode Timing Chart
16
Configuring the Pulse Width Measurement Mode
In this mode, the width of external pulses applied to the
pin-shared external pin PA4/TMR can be measured. In
the Pulse Width Measurement Mode, the timer clock
source is supplied by the internal clock. For the timer to
operate in this mode, bits TM0 and TM1 must both be
set high. If the TE bit is low, once a high to low transition
has been received on the PA4/TMR pin, the timer will
start counting until the PA4/TMR pin returns to its origi-
nal high level. At this point the TON bit will be automati-
cally reset to zero and the timer will stop counting. If the
TE bit is high, the timer will begin counting counting
once a low to high transition has been received on the
PA4/TMR pin and stop counting when the PA4/TMR pin
returns to its original low level. As before, the TON bit
will be automatically reset to zero and the timer will stop
counting. It is important to note that in the Pulse Width
Measurement Mode, the TON bit is automatically reset
to zero when the external control signal on the external
timer pin returns to its original level, whereas in the other
two modes the TON bit can only be reset to zero under
program control. The residual value in the timer, which
can now be read by the program, therefore represents
the length of the pulse received on pin PA4/TMR. As the
TON bit has now been reset any further transitions on
the PA4/TMR pin will be ignored. Not until the TON bit is
again set high by the program can the timer begin fur-
ther pulse width measurements. In this way single shot
pulse measurements can be easily made. It should be
noted that in this mode the counter is controlled by logi-
cal transitions on the PA4/TMR pin and not by the logic
level.
September 19, 2007
HT82J31A