as7c33256pfs18a-166tqi Alliance Memory, Inc, as7c33256pfs18a-166tqi Datasheet - Page 2

• Manufacturer Part Number: as7c33256pfs18a-166tqi
• Description: 3.3v 256k 16/18 Pipeline Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Functional description
The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium
(TMS320C6X), and PowerPC
Fast cycle times of 6/6.7/7.5/10 ns with clock access times (t
Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC),
or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW , the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes
are HIGH. Burst operation is selectable with the
sequence. With
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW , but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW . Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW .
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
•
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33256PFS16A and AS7C33256PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP packaging.
*PowerPC
Capacitance
Write enable truth table (per byte)
Key:
X = Don’t Care, L = Low, H = High, T=True, F=False
* valid read
n = a,b
WE
Input capacitance
I/O capacitance
WE
3/14/01; V.1.0
,
WEn
signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
Parameter
™
= internal write signal
is a tradenark International Business Machines Corporation.
LBO
GWE
H
H
H
L
driven LOW the device uses a linear count sequence suitable for PowerPC
Symbol
C
™
C
I/O
IN
*
-based systems in computing, datacomm, instrumentation, and telecommunications systems.
LBO
Address and control pins
Alliance Semiconductor
input. With
BWE
I/O pins
H
X
L
L
Signals
®
CD
) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
synchronous cache specifications. This architecture is suited for ASIC, DSP
LBO
unconnected or driven HIGH, burst operations use a Pentium
®
BWn
H
X
X
L
™
V
Test conditions
IN
and many other applications.
V
= V
IN
OUT
= 0V
= 0V
AS7C33256PFS16A
AS7C33256PFS18A
WEn
Max
F*
F*
T
T
5
7
P. 2 of 11
Unit
®
pF
pF
count