as7c33256pfs18a-166tqi Alliance Memory, Inc, as7c33256pfs18a-166tqi Datasheet - Page 3

• Manufacturer Part Number: as7c33256pfs18a-166tqi
• Description: 3.3v 256k 16/18 Pipeline Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Signal descriptions
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
3/14/01; V.1.0
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
CE1, CE2
DQ[a,b]
BW[a,b]
A0–A17
Signal
ADSC
ADSP
GWE
BWE
ADV
CLK
LBO
CE0
OE
FT
ZZ
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Parameter
STATIC default =
Properties
CLOCK
ASYNC
ASYNC
STATIC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
HIGH
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When
CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
Synchronous chip enables. Active HIGH and active LOW , respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
Address strobe (processor). Asserted LOW to load a new address or to enter
standby mode.
Address strobe (controller). Asserted LOW to load a new address or to enter
standby mode.
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and
BW[a,b] control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]
inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and
BWE = LOW . If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
in read mode.
Count mode. When driven HIGH, count sequence follows Intel XOR convention.
When driven LOW , count sequence follows linear convention. This signal is
internally pulled HIGH.
Flow-through mode.When LOW , enables single register flow-through mode.
Connect to V
Sleep. Places device in low power mode; data is retained. Connect to GND if
unused.
Alliance Semiconductor
DD
V
if unused or for pipelined operation.
DD
Symbol
I
T
T
V
V
, V
OUT
P
bias
stg
IN
IN
D
DDQ
®
Description
–0.5
–0.5
–0.5
Min
–65
–65
–
–
V
V
DDQ
DD
+150
+135
+4.6
Max
1.8
AS7C33256PFS16A
AS7C33256PFS18A
50
+ 0.5
+ 0.5
P. 3 of 11
Unit
mA
W
V
V
V
C
C