as7c33256ntf3236a ETC-unknow, as7c33256ntf3236a Datasheet
as7c33256ntf3236a
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as7c33256ntf3236a Summary of contents
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November 2004 3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTD Features • Organization: 262,144 words × bits ™ • NTD architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns • Fast OE access time: ...
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Mb Synchronous SRAM products list Org Part Number 512KX18 AS7C33512PFS18A 256KX32 AS7C33256PFS32A 256KX36 AS7C33256PFS36A 512KX18 AS7C33512PFD18A 256KX32 AS7C33256PFD32A 256KX36 AS7C33256PFD36A 512KX18 AS7C33512FT18A 256KX32 AS7C33256FT32A 256KX36 AS7C33256FT36A 512KX18 AS7C33512NTD18A 256KX32 AS7C33256NTD32A 256KX36 AS7C33256NTD36A 512KX18 AS7C33512NTF18A 256KX32 AS7C33256NTF32A 256KX36 AS7C33256NTF36A 1 ...
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Pin arrangement for TQFP (top view) DQPc/NC 1 DQc0 2 DQc1 DDQ V 5 SSQ DQc2 6 DQc3 7 DQc4 8 DQc5 SSQ V 11 DDQ DQc6 12 DQc7 ...
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Functional description The AS7C33256NTF32A/36A family is a high performance CMOS 8 Mbit Synchronous Static Random Access Memory (Flowthrough SRAM) organized as 262,144 words × bits and incorporates a LATE Write. This variation of the 8Mb sychronous SRAM ...
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Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked ...
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Synchronous truth table CE0 CE1 CE2 ADV/LD R ...
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State Diagram for NTD SRAM Read Write 1 Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) ...
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DC electrical characteristics for 3.3V I/O operation Parameter 1 Input leakage current Output leakage current Input high (logic 1) voltage Input low (logic 0) voltage Output high voltage Output low voltage 1 LBO, and ZZ pins have an internal pull-up ...
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Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data Output invalid from clock high Output enable low to output low Z Output enable high to ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t t CENS CENH CEN Address R CSS CSH CE0,CE2 CE1 t t ADVS ADVH ADV/LD OE ...
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Timing waveform of write cycle CLK t t CENH CENS CEN Address R/W BWn t t CSS CSH CE0,CE2 CE1 t t ADVS ADVH ADV/LD OE D(A1) Din t HZOE Dout Q(n-1) DSEL WRITE Command ...
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Timing waveform of read/write cycle CLK t t CENS CENH CEN ADDRESS R BWn t t CSH CSS CE0, CE2 CE1 t t ADVH ADVS ADV/LD ...
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NOP, stall and deselect cycles CLK CEN CE1 CE0, CE2 ADV/LD R/W BWn Address A1 D/Q Q(A1) READ BURST Command Q(A1) Q(A1 Ý Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE ...
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Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 11/8/04, v. 1.1 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only ...
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AC test conditions • Output Load: see Figure B, except for LZC LZOE HZOE HZC • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (Measured at ...
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Package Dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.80 14.20 E 19.80 20.20 e 0.65 nominal c Hd 15.80 16.20 He 21.80 22.20 L 0.45 ...
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O rdering information Package Width TQFP x32 AS7C33256NTF32A-75TQC TQFP x32 AS7C33256NTF32A-75TQI TQFP x36 AS7C33256NTF36A-75TQC TQFP x36 AS7C33256NTF36A-75TQI Note: Add suffix ‘N’ above part numbers for Lead Free Parts (Ex. AS7C33256NTF32A-85TQCN) Part numbering guide AS7C 33 256 1 2 ...
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