as7c33256ntf3236a ETC-unknow, as7c33256ntf3236a Datasheet - Page 6

• Manufacturer Part Number: as7c33256ntf3236a
• Manufacturer: ETC-unknow

Synchronous truth table
Key: X = Don’t Care, H = HIGH, L = LOW.
more byte write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus
will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
balls);
6 All inputs except
7 Wait states are inserted by setting
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
CE0 CE1 CE2 ADV/LD R/W
BW
H
X
X
X
X
X
X
X
X
L
L
L
L
11/8/04, v. 1.1
a enables WRITEs to byte “a” (DQa pins/balls);
BW
X
X
X
H
X
H
X
H
X
H
X
X
L
d enables WRITEs to byte “d” (DQd pins/balls).
X
H
X
X
X
X
X
X
X
L
L
L
L
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
H
H
H
H
H
X
L
L
L
L
L
L
L
CEN
[5,6,7,8,9,11
X
X
X
X
H
X
H
X
X
X
X
L
L
HIGH.
BWn = H means all byte write signals (BWa, BWb, BW
BWn
X
X
X
X
X
X
X
X
H
H
X
L
L
]
BW
OE CEN
b enables WRITEs to byte “b” (DQb pins/balls);
X
X
X
X
H
H
X
X
X
X
X
L
L
Alliance Semiconductor
H
L
L
L
L
L
L
L
L
L
L
L
L
External L to H
External L to H NOP/DUMMY READ (Begin Burst) High-Z
External L to H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z
Address
Current L to H
source
Next
Next
Next
Next
NA
NA
NA
NA
®
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
CLK
DUMMY READ (Continue Burst)
WRITE CYCLE (Continue Burst)
WRITE ABORT (Continue Burst)
CONTINUE DESELECT Cycle
WRITE CYCLE (Begin Burst)
READ Cycle (Continue Burst)
READ Cycle (Begin Burst)
c, and
BW
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
INHIBIT CLOCK
c enables WRITEs to byte “c” (DQc pins/
BW
Operation
AS7C33256NTF32A
AS7C33256NTF36A
d) are HIGH.
BW
n = L means one or
P. 6 of 18
High-Z
High-Z
High-Z
High-Z
High-Z 1,2,10
High-Z
DQ
Q
Q
D
D
-
1,3,10
Notes
1,2,3,
1,10
2,3
10
2
1
3
4