as7c33256ntf3236a ETC-unknow, as7c33256ntf3236a Datasheet - Page 15

• Manufacturer Part Number: as7c33256ntf3236a
• Manufacturer: ETC-unknow

AC test conditions
• Output Load: see Figure B,
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
except for
11/8/04, v. 1.1
+3.0V
GND
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C
This parameter is sampled and not 100% tested.
t
t
I
Transitions are measured ±500 mV from steady state voltage. Output loading specified with C
t
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs mus
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
HZOE
CH
HZCN
CC
Figure A: Input waveform
10%
given with no output loading. I
measured as high above VIH, and t
90%
is less than t
is a
t
LZC
‘no load’ parameter to indicate exactly when SRAM outputs have stopped driving.
, t
LZOE
LZOE
; and t
, t
90%
HZOE
10%
HZC
, t
is less than t
CC
HZC
increases with faster cycle times and greater output loading.
CL
see Figure C.
measured as low below VIL
D
out
LZC
at any given temperature and voltage.
Figure B: Output load (A)
Z
0
=50
Alliance Semiconductor
Ω
50
30 pF*
Ω
®
V
L
=1.5V
353Ω/1538Ω
L
= 5 pF as in Figure C.
D
OUT
Figure C: Output load(B)
AS7C33256NTF32A
AS7C33256NTF36A
Thevenin equivalent:
319Ω/1667Ω
5 pF*
GND
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
*including scope
and jig capacitance
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