wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 164

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
w
R08 (08h)
Clocking (2)
REGISTER
ADDRESS
12:9
8:6
5
4:1
0
15
14
13
BIT
OPCLKDIV
[3:0]
DCLKDIV
[2:0]
BCLK_DIV
[3:0]
MCLK_SRC
SYSCLK_SRC
CLK_FORCE
LABEL
0000b
111b
0b
0100b
0b
0b
0b
0b
DEFAULT
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
Class D Clock Divider
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
Reserved - Do Not Change
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCLK / 48
Reserved - Do Not Change
MCLK Source Select
0 = MCLK pin
1 = GPIO2/MCLK2 pin
SYSCLK Source Select
0 = MCLK (or MCLK2 if MCLK_SRC=1)
1 = FLL output
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK, MCLK2 or FLL output)
must be active when changing to a new clock source.
1 = Allows existing MCLK source to be disabled before
changing to a new clock source.
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
164