wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 44

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
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Two clocking modes are provided - Normal Mode (AIF_LRCLKRATE = 0) allows selection of the
commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB
Mode (AIF_LRCLKRATE = 1) allows many of these sample rates to be generated from a 12MHz
USB clock. Depending on the available clock sources, the USB mode may be used to save power by
supporting 44.1kHz operation without recourse to the FLL.
The AIF_LRCLKRATE field must be set as described in Table 8 to ensure correct operation of
internal functions according to the SYSCLK / Fs ratio. Table 9 describes the available sample rates
using four different common MCLK frequencies.
In Normal mode, the programmable division set by ADC_CLKDIV must ensure that a 256 * ADC Fs
clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 256 * DAC Fs clock is
generated for the DAC DSP.
In USB mode, the programmable division set by ADC_CLKDIV must ensure that a 272 * ADC Fs
clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 272 * DAC Fs clock is
generated for the DAC DSP.
Note that in USB mode, the ADC / DAC sample rates do not match exactly with the commonly used
sample rates (e.g. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%.
Data recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub
0.5%) pitch shift as a result of this difference. Note also that the USB mode cannot be used to
generate a 48kHz samples rate from a 12MHz MCLK; the FLL should be used in this case.
In low sample rate modes (eg. 8kHz voice), the SNR is liable to be degraded if the typical 64fs DAC
clocking rate is used (see Figure 17). In this case, it may be possible to improve the SNR by raising
the DAC clocking rate by setting the DAC_SDMCLK_RATE register field, causing the DAC clocking
rate to be set equal to SYSCLK/4. The DAC_CLKDIV field must still be set as described above to
derive the correct clock for the DAC DSP. In 8kHz voice applications, in systems where SYSCLK >
256fs (or 272fs when applicable), setting DAC_SDMCLK_RATE will result in the SNR performance
being improved. Note that setting DAC_SDMCLK_RATE will result in an increase in power
consumption.
Table 8 ADC / DAC Sample Rate Control
R8 (08h)
R11 (0Bh)
REGISTER
ADDRESS
7:5
4:2
13
10
BIT
ADC_CLKDIV
[2:0]
DAC_CLKDIV
[2:0]
DAC_SDMCLK_
RATE
AIF_LRCLKRATE
LABEL
DEFAULT
000b
000b
0b
0b
ADC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
DAC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
DAC clocking rate
0 = Normal operation (64fs)
1 = SYSCLK/4
LRCLK Rate
0 = Normal mode (256 * fs)
1 = USB mode (272 * fs)
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
44