wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 41

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

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Pre-Production
Figure 16 3-Wire Serial Control Interface
Auto-increment mode is only supported when enabled by setting the AUTOINC register bit.
Alert Response Address protocol is supported by the WM8400 when the ARA_ENA register bit is
set. This function enables a bus controller to poll multiple devices on the I2C bus simultaneously in
order to respond to Interrupt events efficiently. The WM8400 device address used by this protocol is
set as described in Table 4.
Table 5 2-Wire Control Interface Configuration
3-WIRE SERIAL CONTROL MODE
The WM8400 is controlled by writing to registers through a 3-wire serial control interface. A control
word consists of 24 bits. The first bit is the read/write bit (R/W), which is followed by 7 address bits
(A6 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are
data bits, corresponding to the 16 bits in each control register.
In 3-wire control mode, the SPI_CFG register bit can be used to select between push 0/1 and open-
drain modes, as described in Table 6 below.
Table 6 3-Wire Control Interface Configuration
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
NCSADDR latches in a complete control word consisting of the last 24 bits.
In Write operations (R/W=0), all SDIN bits are driven by the controlling device.
In Read operations (R/W=1), the SDIN pin is driven by the controlling device to clock in the register
address, after which the WM8400 drives the SDIN pin to output the applicable data bits.
The 3-wire control mode timing is illustrated in Figure 16.
R75 (4Bh)
R75 (4Bh)
REGISTER
REGISTER
ADDRESS
ADDRESS
3
2
BIT
BIT
1
AUTOINC
ARA_ENA
SPI_CFG
LABEL
LABEL
1b
0b
DEFAULT
DEFAULT
0b
Enable Auto-Increment function (2-wire
I2C mode)
0 = Disabled
1 = Enabled
Enable Alert Response Address function
(2-wire I2C mode)
0 = Disabled
1 = Enabled
3-wire Read mode configuration
0 = CMOS output
1 = Open-drain
DESCRIPTION
DESCRIPTION
PP, April 2009, Rev 3.0
WM8400
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