wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 165

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

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Pre-Production
R09 (09h)
Audio
Interface (3)
REGISTER
ADDRESS
12:11
10
9:8
7:5
4:2
1:0
15
14
13
12
11
10:0
BIT
MCLK_DIV
[1:0]
MCLK_INV
ADC_CLKDIV
[2:0]
DAC_CLKDIV
[2:0]
AIF_MSTR1
AIF_MSTR2
AIF_SEL
ADCLRC_DIR
ADCLRC_RATE
[10:0]
LABEL
00b
0b
00b
000b
000b
00b
0b
0b
0b
0b
0b
040h
DEFAULT
SYSCLK Pre-divider. Clock source (MCLK, MCLK2 or FLL
output) will be divided by this value to generate SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
MCLK Invert
0 = Master clock (MCLK or MCLK2) not inverted
1 = Master clock (MCLK or MCLK2) inverted
Reserved - Do Not Change
ADC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
DAC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
Reserved - Do Not Change
Audio Interface 1 Master Mode Select
0 = Slave mode
1 = Master mode
Audio Interface 2 Master Mode Select
0 = Slave mode
1 = Master mode
Audio Interface Select
0 = Audio interface 1
1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2,
GPIO5/DACDAT2)
Reserved - Do Not Change
ADCLRC Direction
(Forces ADCLRC clock to be output in slave mode)
0 = ADCLRC normal operation
1 = ADCLRC clock output enabled
ADCLRC Rate
ADCLRC clock output = BCLK / ADCLRC_RATE
Integer (LSB = 1)
Valid from 8..2047
DESCRIPTION
PP, April 2009, Rev 3.0
WM8400
165