srf-2724cs RF Micro Devices, srf-2724cs Datasheet - Page 14

• Manufacturer Part Number: srf-2724cs
• Description: 2.4ghz Low-if 1.5mbps Fsk Transceiver
• Manufacturer: RF Micro Devices

SRF-2724CS
PLL Programming and Channel Selection
The SRF-2724CS PLL is programmed via control register 2 to the set RF center frequency of operation of the radio. The PLL
does not need to be (though it can be) reprogrammed between RECEIVE and TRANSMIT modes. Nominal channel separation is
2.048MHz, allowing for over 40 non-overlapping channels in any given location. With careful planning, channels can be pro-
grammed in 1024kHz steps as long as care is exercised to insure that two radio links will not share spectrum at any one time.
The equation to determine channel center frequency from the SRF-2724CS control register word is:
fC = CHQ<0:11>*1.024MHz
Standby Mode
In STANDBY mode, the SRF-2724CS transceiver is powered down. The only circuits active are the control interfaces, which are
digital CMOS to minimize power consumption. The serial control interface and control registers remain powered up and will
accept and retain programming data as long as the digital supply is present. When exiting STANDBY mode, the device may
need to be kept in RECEIVE mode for up to 256μs to allow for filter self-calibration.
DATA INTERFACE
There are two control interfaces: CONTROL and SERIAL.
CONTROL Interface
The control interface provides immediate control and monitoring of the SRF-2724CS. Input signals include:
• XCEN:Transceiver enable. Places the SRF-2724CS in Standby or Active (when asserted) modes.
• RXON:Receive On. Places an Active SRF-2724CS in Receive mode when asserted.
• FREF:Reference frequency input
Output signals include:
• RSSI:Received Signal Strength Indicator: indicates the power of the received signal
• PAON:External Power Amplifier Control Pin
SERIAL Interface
A 3-wire serial interface (EN, DATA, CLK) is used for programming the SRF-2724CS configuration registers, which control device
mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are entered beginning
with the MSB (“big-endian”). The word is divided into a leading 14-bit data field followed by a 2-bit address field. When the
address field has been decoded the destination register is loaded on the rising edge of EN. Providing less than 16 bits of data
will result in unpredictable behavior when EN goes high.
Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift register on the
rising edge of the CLK pin. This information is loaded into the target control register when EN goes high. This serial interface
bus is similar to that commonly found on PLL devices. It can be efficiently programmed by either byte or 16-bit word oriented
serial bus hardware. The data latches are implemented in CMOS and use minimal power when the bus is inactive. Refer to Fig-
ure 4 and Table 2: 3-Wire Bus Timing Characteristics for timing and register programming illustrations.
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