srf-2724cs RF Micro Devices, srf-2724cs Datasheet - Page 18

• Manufacturer Part Number: srf-2724cs
• Description: 2.4ghz Low-if 1.5mbps Fsk Transceiver
• Manufacturer: RF Micro Devices

SRF-2724CS
Table 5: Register 2 - Test Mode Register
Power-On State
On Power up, all register bits are cleared to the default value of 0 (zero). Power up is defined as occurring when VDD >2.0V.
The register default values are valid upon power up.
CONTROL REGISTER BIT DESCRIPTIONS
ADR <1:0>, All Registers, Bits 0-1
Address Bits: The ADR<1:0> bits are the least-significant bits of each register. Each register is divided into a data field and an
address field. The data field is the leading field, while the last two bits clocked into the register are always the address field.
When EN goes high, the address field is decoded and the addressed destination register is loaded. The last 16 bits clocked
into the serial bus are loaded into the register. Clocking in less than 16 bits results in a potentially incorrect entry into the reg-
ister.
RES (Reserved), All Registers
Reserved Bits: These bits are reserved. These bits must be cleared to 0s (zeros) for normal operation. When power is reset, all
of the registers’ data fields are cleared to 0s (zeros).
QPP - Register 0, Bit 2
Charge Pump Polarity: This bit sets the charge pump polarity to sink or source current. For a majority of applications, this bit is
cleared (QPP=0). For applications where an external inverting amplifier is used in the loop filter, this bit is set to change the
charge pump polarity (see Table 6).
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Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
DTM2
DTM1
DTM0
ATM2
ATM1
ATM0
ADR1
ADR0
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Table 6: PLL Charge Pump Polarity
Analog Test Control Bits
Digital Test Control Bits
QPP
0
1
MSB Address Bit
LSB Address Bit
Description
Reserved
f
c
f
PLL Charge Pump Polarity
>f
c
>f
ref
ref
=Charge pump sources current
=Charge pump sinks current
Proposed
Set all bits to 0 (zero)
See Table 16
See Table 15
Definition
ADR1=0
ADR0=1
Prelim DS090410