laxp2-17e Lattice Semiconductor Corp., laxp2-17e Datasheet
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LA-LatticeXP2™ Family Data Sheet Preliminary DS1024 Version 01.0, June 2008 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Introduction LA-LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an archi- tecture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LA-LatticeXP2-17 Device (Top Level) On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysMEM Block RAM DSP Blocks sysCLOCK PLLs PFU Blocks The core of the LA-LatticeXP2 device is made up of logic blocks ...
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Lattice Semiconductor Figure 2-2. PFU Diagram LUT4 & LUT4 & CARRY CARRY Slice Slice Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3 contains two LUT4s ...
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Lattice Semiconductor Figure 2-3. Slice Diagram FXB FXA From Routing CLK LSR * Not in Slice 3 For Slices 0 and 2, memory control signals are generated from Slice ...
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Lattice Semiconductor Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input ...
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Lattice Semiconductor Routing There are many resources provided in the LA-LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are ...
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Lattice Semiconductor Figure 2-4. General Purpose PLL (GPLL) Diagram WRDEL DDUTY DPHASE CLKI CLKI Divider CLKFB CLKFB Divider RSTK RST Table 2-4 provides a description of the signals in the GPLL blocks. Table 2-4. GPLL Block Signal Descriptions Signal I/O ...
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Lattice Semiconductor Figure 2-5. Clock Divider Connections CLKOP (GPLL) Clock Distribution Network LA-LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based secondary clocks/control signals. Two high performance edge clocks are available on each edge of ...
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Lattice Semiconductor Figure 2-6. Primary Clock Sources for LatticeXP2-17 PLL Input GPLL CLK DIV Clock Input Clock Input PLL Input GPLL Note: This diagram shows sources for the LA-LatticeXP2-17 device. Smaller LA-LatticeXP2 devices have two GPLLs. LA-LatticeXP2 Family Data Sheet ...
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Lattice Semiconductor Secondary Clock/Control Sources LA-LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources From Routing From Routing ...
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Lattice Semiconductor Edge Clock Sources Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown ...
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Lattice Semiconductor Primary Clock Routing The clock routing structure in LA-LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center ...
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Lattice Semiconductor LatticeXP2 devices have six secondary clock regions and eight secondary clocks (SC0 to SC7) which are distrib- uted to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux ...
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Lattice Semiconductor Slice Clock Selection Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice 0 through Slice 2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. ...
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Lattice Semiconductor Figure 2-15. Edge Clock Mux Connections GPLL Output CLKOP GPLL Output CLKOS sysMEM Memory LA-LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit RAM with dedicated input and output registers. ...
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Lattice Semiconductor Table 2-5. sysMEM Block Configurations Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to ...
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Lattice Semiconductor EBR memory supports two forms of write behavior for single port or dual port operation: 1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) ...
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Lattice Semiconductor If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f release ...
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Lattice Semiconductor mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can be concatenated. The resources in each sysDSP block can be configured to support the following four elements: • MULT (Multiply) ...
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Lattice Semiconductor Figure 2-20. MULT sysDSP Element Shift Register B In Multiplicand Multiplier n Input Data Register B Signed A Signed B Shift Register B Out Shift Register Multiplier m Input Data Register A ...
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Lattice Semiconductor MAC sysDSP Element In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input ...
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Lattice Semiconductor MULTADDSUB sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and B1. The user can enable the input, output ...
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Lattice Semiconductor MULTADDSUBSUM sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and B1. Additionally the operands A2 and B2 are ...
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Lattice Semiconductor register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. Signed and Unsigned with Different Widths The DSP ...
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Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure each DSP module (or group of modules direct HDL instantiation. In addition, Lattice has partnered with The ...
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Lattice Semiconductor Figure 2-25. PIC Diagram TD OPOS1 ONEG1 OPOS0 OPOS2 1 ONEG0 ONEG2 1 1 QNEG0 1 QNEG1 1 QPOS0 QPOS1 1 INCK 2 INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN ECLK1 ECLK2 DDRCLKPOL 1 DQSXFER 1 DQS ...
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Lattice Semiconductor Table 2-11. PIO Signal List Name Type CE Control from the core CLK Control from the core ECLK1, ECLK2 Control from the core LSR Control from the core GSRN Control from routing 2 INCK Input to the core ...
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Lattice Semiconductor The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade- quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic, see the ...
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Lattice Semiconductor shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High Speed I/O Interface. Figure 2-27. Output and Tristate Block TD Tristate Logic ONEG1 OPOS1 Q ONEG0 D * D-Type OPOS0 Q ...
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Lattice Semiconductor Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation and ...
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Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) DQS Figure 2-29. DQS Input Routing (Top and Bottom) DQS LA-LatticeXP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" PIO A LVDS Pair ...
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Lattice Semiconductor DLL Calibrated DQS Delay Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in ...
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Lattice Semiconductor Figure 2-31. DQS Local Bus *DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO. Polarity Control Logic In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and ...
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Lattice Semiconductor DQSXFER LA-LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90 DQSXFER signal runs the span of the data bus. sysIO Buffer ...
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Lattice Semiconductor LA-LatticeXP2 devices contain two types of sysIO buffer pairs. 1. Top and Bottom (Banks and 5) sysIO Buffer Pairs (Single-Ended Outputs Only) The sysIO buffer pairs in the top banks of the device consist of ...
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Lattice Semiconductor Table 2-12. Supported Input Standards Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 HSTL18 Class I, II HSTL15 Class I SSTL33 Class I, II SSTL25 Class I, II SSTL18 Class I, II Differential Interfaces ...
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Lattice Semiconductor Table 2-13. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II HSTL15 Class I ...
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Lattice Semiconductor be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has ...
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Lattice Semiconductor 1. Unlocked 2. Key Locked – Presenting the key through the programming interface allows the device to be unlocked. 3. Permanently Locked – The device is permanently locked. To further complement the security of the device a One ...
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Lattice Semiconductor to the original backup configuration and try again. This all can be done without power cycling the system. For more information please see TN1144, LatticeXP2 Dual Boot Usage Guide. For more information on device configuration, please see TN1141, ...
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Lattice Semiconductor Density Shifting The LA-LatticeXP2 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration ...
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... Data Retention RETENTION © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Hot Socketing Specifications Symbol Parameter I Input or I/O Leakage Current DK 1. Insensitive to sequence CCAUX 2. 0 ≤ V ≤ V (MAX), 0 ≤ V ≤ CCIO CCIO ...
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Lattice Semiconductor Supply Current (Standby) Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (per PLL) CCPLL I Bank Power Supply Current (per bank) CCIO I V Power Supply Current CCJ ...
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Lattice Semiconductor Initialization Supply Current Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (per PLL) CCPLL I Bank Power Supply Current (per Bank) CCIO I VCCJ Power Supply Current CCJ ...
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Lattice Semiconductor Programming and Erase Flash Supply Current Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (per PLL) CCPLL I Bank Power Supply Current (per Bank) CCIO I V Power ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. 2 LVCMOS33 3.135 2 LVCMOS25 2.375 LVCMOS18 1.71 LVCMOS15 1.425 2 LVCMOS12 1.14 2 LVTTL33 3.135 PCI33 3.135 2 SSTL18_I , 1.71 2 SSTL18_II 2 SSTL25_I , 2.375 2 SSTL25_II 2 SSTL33_I ...
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Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS33 -0.3 0.8 LVTTL33 -0.3 0.8 LVCMOS25 -0.3 0.7 LVCMOS18 -0.3 0.35 V LVCMOS15 -0.3 0.35 V LVCMOS12 -0.3 0.35 V PCI33 -0.3 0.3 V ...
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Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Description Input Voltage INP INM V Input Common Mode Voltage CM V Differential Input Threshold THD I Input Current IN V Output High Voltage for Output ...
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Lattice Semiconductor Table 3-1. LVDS25E DC Conditions Parameter V Output Driver Supply (+/-5%) CCIO Z Driver Impedance OUT R Driver Series Resistor (+/-1 Driver Parallel Resistor (+/-1 Receiver Termination (+/-1 Output High Voltage (after ...
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Lattice Semiconductor BLVDS The LA-LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point ...
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Lattice Semiconductor LVPECL The LA-LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using comple- mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan- dard is supported by the LVDS ...
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Lattice Semiconductor RSDS The LA-LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input ...
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Lattice Semiconductor MLVDS The LA-LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential ...
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Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register-to-Register Performance Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX ...
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Lattice Semiconductor Register-to-Register Performance (Continued) DSP IP Functions 16-Tap Fully-Parallel FIR Filter 1024-pt FFT 8X8 Matrix Multiplication 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device, design and tool version. The tool ...
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Lattice Semiconductor LA-LatticeXP2 External Switching Characteristics Parameter General I/O Pin Parameters (using Primary Clock without PLL) t Clock to Output - PIO Output Register CO t Clock to Data Setup - PIO Input Register SU t Clock to Data Hold ...
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Lattice Semiconductor LA-LatticeXP2 External Switching Characteristics (Continued) Parameter t Clock to Data Hold - PIO Input Register HPLL t Clock to Data Setup - PIO Input Register with Data Input Delay SU_DELPLL t Clock to Data Hold - PIO Input ...
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Lattice Semiconductor LA-LatticeXP2 Internal Switching Characteristics Parameter PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU (Asynchronous) ...
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Lattice Semiconductor LA-LatticeXP2 Internal Switching Characteristics Parameter t Hold Write/Read Enable to EBR Memory (Write/Read Clk) HWREN_EBR t Clock Enable Setup Time to EBR Output Register (Read Clk) SUCE_EBR t Clock Enable Hold Time to EBR Output Register (Read Clk) ...
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Lattice Semiconductor EBR Timing Diagrams Figure 3-6. Read/Write Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after ...
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Lattice Semiconductor Figure 3-8. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA Data from Prev Read DOA or Write Note: Input data and address are registered at the positive ...
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Lattice Semiconductor LA-LatticeXP2 Family Timing Adders Buffer Type Input Adjusters LVDS25 LVDS BLVDS25 BLVDS MLVDS LVDS RSDS RSDS LVPECL33 LVPECL HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class II ...
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Lattice Semiconductor LA-LatticeXP2 Family Timing Adders Buffer Type HSTL15_I HSTL_15 class I 4mA drive HSTL15D_I Differential HSTL 15 class I 4mA drive SSTL33_I SSTL_3 class I SSTL33_II SSTL_3 class II SSTL33D_I Differential SSTL_3 class I SSTL33D_II Differential SSTL_3 class II ...
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Lattice Semiconductor LA-LatticeXP2 Family Timing Adders Buffer Type LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate LVCMOS25_20mA LVCMOS 2.5 20mA drive, slow slew rate ...
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Lattice Semiconductor sysCLOCK PLL Timing Parameter Description f Input Clock Frequency (CLKI, CLKFB) IN Output Clock Frequency (CLKOP, f OUT CLKOS) f K-Divider Output Frequency OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t ...
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Lattice Semiconductor LA-LatticeXP2 sysCONFIG Port Timing Specifications Parameter sysCONFIG POR, Initialization and Wake Up t Minimum Vcc to INITN High ICFG t Time from tICFG to valid Master CCLK VMC t PROGRAMN Pin Pulse Rejection PRGMRJ t PROGRAMN Low Time ...
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Lattice Semiconductor On-Chip Oscillator and Configuration Master Clock Characteristics Parameter Master Clock Frequency Duty Cycle Timing v. A 0.11 Figure 3-9. Master SPI Configuration Waveforms Capture CR0 VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI Over Recommended Operating Conditions Min. ...
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Lattice Semiconductor Flash Download Time (from On-Chip Flash to SRAM) Symbol PROGRAMN Low-to- High. Transition to Done High. t REFRESH Power-up refresh when PROGRAMN is pulled Min Flash Program Time Device LA-XP2-5 ...
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Lattice Semiconductor JTAG Port Timing Specifications Symbol f TCK Clock Frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time ...
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Lattice Semiconductor Switching Test Conditions Figure 3-11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-11. Output Test Load, LVTTL ...
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... TCK TDI © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Signal Descriptions (Cont.) Signal Name TDO VCCJ Configuration Pads (Used during sysCONFIG) CFG[1:0] 1 INITN PROGRAMN DONE CCLK 2 SISPI 2 SOSPI 2 CSSPIN CSSPISN TOE 1. If not actively driven, the internal pull-up may not be sufficient. ...
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Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe For Left and Right Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] ...
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Lattice Semiconductor Pin Information Summary Pin Type Single Ended User I/O Normal Differential Pair User I/O Highspeed TAP Configuration Muxed Dedicated Muxed Non Configuration Dedicated Vcc Vccaux VCCPLL Bank0 Bank1 Bank2 Bank3 VCCIO Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 NC ...
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Lattice Semiconductor Pin Information Summary (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 DDR Banks Bonding Out 1 per I/O Bank Bank4 Bank5 Bank6 Bank7 Bank0 Bank1 Bank2 Bank3 PCI capable I/Os Bonding Out per Bank Bank4 Bank5 Bank6 Bank7 1. ...
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... The specifications and information herein are subject to change without notice. www.latticesemi.com LA-LatticeXP2 Family Data Sheet Ordering Information Grade E = Automotive Package TN144 = 144-pin Lead-Free TQFP QN208 = 208-pin Lead-Free PQFP FTN256 = 256-ball Lead-Free ftBGA XP2 LAXP2-17E 5FT256E Datecode 5-1 Preliminary Data Sheet DS1024 Order Info_01.0 ...
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... Voltage LAXP2-5E-5TN144E 1.2V LAXP2-5E-5QN208E 1.2V LAXP2-5E-5FTN256E 1.2V Part Number Voltage LAXP2-8E-5TN144E 1.2V LAXP2-8E-5QN208E 1.2V LAXP2-8E-5FTN256E 1.2V Part Number Voltage LAXP2-17E-5QN208E 1.2V LAXP2-17E-5FTN256E 1.2V LA-LatticeXP2 Family Data Sheet Grade Package Pins -5 Lead-Free TQFP 144 -5 Lead-Free PQFP 208 -5 Lead-Free ftBGA 256 Grade Package Pins -5 Lead-Free TQFP ...
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... PCI: www.pcisig.com © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... June 2008 01.0 © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...