laxp2-17e Lattice Semiconductor Corp., laxp2-17e Datasheet - Page 11

• Manufacturer Part Number: laxp2-17e
• Description: Latticexp2 Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2-5. Clock Divider Connections
Clock Distribution Network
LA-LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based
secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to
support high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing.
Clock inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LA-LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock
inputs and routing. LA-LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the
device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock
sources.
CLKOP (GPLL)
ECLK
RELEASE
RST
2-8
CLKDIV
LA-LatticeXP2 Family Data Sheet
÷1
÷2
÷4
÷8
Architecture