laxp2-17e Lattice Semiconductor Corp., laxp2-17e Datasheet - Page 28

• Manufacturer Part Number: laxp2-17e
• Description: Latticexp2 Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
IPexpress™
The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure
each DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The
MathWorks
ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LA-LatticeXP2 DSP
include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and
Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores.
Resources Available in the LA-LatticeXP2 Family
Table 2-8 shows the maximum number of multipliers for each member of the LA-LatticeXP2 family. Table 2-9 shows
the maximum available EBR RAM Blocks and Serial TAG Memory bits in each LA-LatticeXP2 device. EBR blocks,
together with Distributed RAM can be used to store variables locally for fast DSP operations.
Table 2-8. Maximum Number of DSP Blocks in the LA-LatticeXP2 Family
Table 2-9. Embedded SRAM/TAG Memory in the LA-LatticeXP2 Family
LA-LatticeXP2 DSP Performance
Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of
the LA-LatticeXP2 family.
Table 2-10. DSP Performance
For further information on the sysDSP block, please see TN1140, LatticeXP2 sysDSP Usage Guide.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the
buffer. Table 2-11 provides the PIO signal list.
LA-XP2-17
LA-XP2-5
LA-XP2-8
Device
®
to support instantiation in the Simulink
LA-XP2-17
LA-XP2-5
LA-XP2-8
Device
DSP Block
LA-XP2-17
LA-XP2-5
LA-XP2-8
Device
3
4
5
EBR SRAM Block
12
15
9
9x9 Multiplier
®
DSP Block
tool, a graphical simulation environment. Simulink works with
2-25
24
32
40
3
4
5
Total EBR SRAM
(Kbits)
166
221
276
DSP Performance
LA-LatticeXP2 Family Data Sheet
18x18 Multiplier
MMAC
3,900
5,200
6,500
12
16
20
TAG Memory
(Bits)
2184
632
768
36x36 Multiplier
Architecture
3
4
5