laxp2-17e Lattice Semiconductor Corp., laxp2-17e Datasheet - Page 16

• Manufacturer Part Number: laxp2-17e
• Description: Latticexp2 Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
LatticeXP2 devices have six secondary clock regions and eight secondary clocks (SC0 to SC7) which are distrib-
uted to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for high fan-out control and SC4 to SC7 are used
for clock signals.
Figure 2-11. Secondary Clock Regions LatticeXP2-17
Figure 2-12. Secondary Clock Selection
Secondary Clock
Secondary Clock
Secondary Clock
SC0
4:1
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
SC1
4:1
Secondary Clock Sources: 8 PIOs + 16 Routing
SC2
4:1
8 Secondary Clocks (SC0 to SC7)
SC3
4:1
Clock/Control
Secondary Clock
Secondary Clock
Secondary Clock
2-13
I/O Bank 1
I/O Bank 4
Region 6
Region 5
Region 4
SC4
4:1
SC5
4:1
LA-LatticeXP2 Family Data Sheet
SC6
4:1
SC7
4:1
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
Architecture