cn8236 Mindspeed Technologies, cn8236 Datasheet

cn8236

Manufacturer Part Number

cn8236

Description

Atm Servicesar Plus With Xbr Traffic Management

Manufacturer

Mindspeed Technologies

Datasheet

1.CN8236.pdf (443 pages)

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CN8236

ATM ServiceSAR Plus with xBR Traffic Management

The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal

functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface

with service-specific functions in a single package for AAL0, 3/4, and 5 operations.

The ServiceSAR Controller generates and terminates ATM traffic and automatically

schedules cells for transmission. The CN8236 is targeted at 155 Mbps throughput

systems where the number of VCCs is relatively large, or the performance of the overall

system is critical. Examples of such networking equipment include Routers, Ethernet

switches, ATM Edge switches, or Frame Relay switches.

Service-Specific Performance Accelerators

The CN8236 incorporates numerous service-specific features designed to accelerate

and enhance system performance. As examples, the CN8236 implements Echo

Suppression of LAN traffic via LECID filtering, and supports Frame Relay DE to CLP

interworking.

Advanced xBR Traffic Management

The xBR Traffic Manager in the CN8236 supports multiple ATM service categories. This

includes CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed Frame

Rate), and ABR. The CN8236 manages each VCC independently. It dynamically

schedules segmentation traffic to comply with up to 16+CBR user-configured

scheduling priorities for the various traffic classes. Scheduling is controlled by a

Schedule table configured by the user and based on a user-specified time reference.

ABR channels are managed in hardware according to user-programmable ABR

templates. These templates tune the performance of the CN8236’s ABR algorithms to a

specific system’s or network’s requirements.

Functional Block Diagram

Data Sheet

Multi-client

PCI Bus

Master/

Slave

PCI

Counters

Timer

Proc'r

DMA

Co-

Local Memory

Coprocessor

Segmentation

CBR, VBR, ABR,

Reassembly

Interface

Coprocessor

UBR, GFR

Local Bus

Traffic Manager

Control/

Status

FIFO

Cell

CN8236

–Continued–

Patent Pending

Rx/Tx

UTOPIA

Master/Slave

Distinguishing Features

Service-Specific Performance

Accelerators

• LECID filtering and echo suppression

• Dual leaky bucket based on CLP

• Frame relay DE interworking

• Internal SNMP MIB counters

• IP over ATM; supports both CLP0+1

Flexible Architectures

• Multi-peer host

• Direct switch attachment via reverse

• ATM terminal

• Optional local processor

CN8250

(frame relay)

and ABR shaping

UTOPIA

– Host control

– Local bus control

Device

PHY

28236-DSH-001-B

–Continued–

May 2003

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